Issued Patents All Time
Showing 101–115 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7941644 | Simultaneous multi-thread instructions issue to execution units while substitute injecting sequence of instructions for long latency sequencer instruction via multiplexer | Eric O. Mejdrich, Matthew R. Tubbs | 2011-05-10 |
| 7926009 | Dual independent and shared resource vector execution units with shared register file | Eric O. Mejdrich, Matthew R. Tubbs | 2011-04-12 |
| 7921278 | Early exit processing of iterative refinement algorithm using register dependency disable | Matthew R. Tubbs | 2011-04-05 |
| 7913066 | Early exit processing of iterative refinement algorithm using register dependency disable and programmable early exit condition | Matthew R. Tubbs | 2011-03-22 |
| 7904700 | Processing unit incorporating special purpose register for use with instruction-based persistent vector multiplexer control | Eric O. Mejdrich, Robert A. Shearer, Matthew R. Tubbs | 2011-03-08 |
| 7904699 | Processing unit incorporating instruction-based persistent vector multiplexer control | Eric O. Mejdrich, Robert A. Shearer, Matthew R. Tubbs | 2011-03-08 |
| 7890699 | Processing unit incorporating L1 cache bypass | Miguel Comparan, Eric O. Mejdrich | 2011-02-15 |
| 7873066 | Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip | Robert A. Shearer, Matthew R. Tubbs | 2011-01-18 |
| 7868894 | Operand multiplexor control modifier instruction in a fine grain multithreaded vector microprocessor | Eric O. Mejdrich, Matthew R. Tubbs | 2011-01-11 |
| 7814299 | Designating operands with fewer bits in instruction code by indexing into destination register history table for each thread | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2010-10-12 |
| 7814303 | Execution of a sequence of vector instructions preceded by a swizzle sequence instruction specifying data element shuffle orders respectively | Robert A. Shearer, Matthew R. Tubbs | 2010-10-12 |
| 7809925 | Processing unit incorporating vectorizable execution unit | Eric O. Mejdrich, Matthew R. Tubbs | 2010-10-05 |
| 7783860 | Load misaligned vector with permute and mask insert | David Arnold Luick, Eric O. Mejdrich | 2010-08-24 |
| 7737974 | Reallocation of spatial index traversal between processing elements in response to changes in ray tracing graphics workload | Eric O. Mejdrich, Robert A. Shearer | 2010-06-15 |
| 7234017 | Computer system architecture for a processor connected to a high speed bus transceiver | Giora Biran, Matthew Adam Cushing, Robert Allen Drehmel, Allen James Gavin, Mark E. Kautzman +8 more | 2007-06-19 |