Issued Patents All Time
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11074205 | Managing efficient selection of a particular processor thread for handling an interrupt | Richard Louis Arndt, Florian A. Auernhammer, Wayne M. Barrett, Guy L. Guthrie, Michael S. Siegel +1 more | 2021-07-27 |
| 10565140 | Techniques for issuing interrupts in a data processing system with multiple scopes | Florian A. Auernhammer, Wayne M. Barrett, Michael S. Siegel | 2020-02-18 |
| 10552351 | Techniques for issuing interrupts in a data processing system with multiple scopes | Florian A. Auernhammer, Wayne M. Barrett, Michael S. Siegel | 2020-02-04 |
| 10423550 | Managing efficient selection of a particular processor thread for handling an interrupt | Richard Louis Arndt, Florian A. Auernhammer, Wayne M. Barrett, Guy L. Guthrie, Michael S. Siegel +1 more | 2019-09-24 |
| 10210112 | Techniques for issuing interrupts in a data processing system with multiple scopes | Florian A. Auernhammer, Wayne M. Barrett, Michael S. Siegel | 2019-02-19 |
| RE44342 | Bus architecture employing varying width uni-directional command bus | Kent Harold Haselhorst, Russel Dean Hoover, James Anthony Marcella | 2013-07-02 |
| 8069353 | Low-latency data decryption interface | Bruce Beukema, William E. Hall, Jamie R. Kuesel, Gilad Pivonia, Robert A. Shearer | 2011-11-29 |
| 7873773 | Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes | Gerald K. Bartley, John Michael Borkenhagen, James Anthony Marcella | 2011-01-18 |
| 7757032 | Computer system bus bridge | Giora Biran, Robert S. Horton, Mark E. Kautzman, Jamie R. Kuesel, Ming-i Mark Lin +3 more | 2010-07-13 |
| 7469312 | Computer system bus bridge | Giora Biran, Robert S. Horton, Mark E. Kautzman, Jamie R. Kuesel, Ming-i Mark Lin +3 more | 2008-12-23 |
| 7461268 | E-fuses for storing security version data | William E. Hall, Russell D. Hoover | 2008-12-02 |
| 7409558 | Low-latency data decryption interface | Bruce Beukema, William E. Hall, Jamie R. Kuesel, Gilad Pivonia, Robert A. Shearer | 2008-08-05 |
| 7275125 | Pipeline bit handling circuit and method for a bus bridge | Clarence R. Ogilvie, Charles S. Woodruff | 2007-09-25 |
| 7254663 | Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes | Gerald K. Bartley, John Michael Borkenhagen, James Anthony Marcella | 2007-08-07 |
| 7234017 | Computer system architecture for a processor connected to a high speed bus transceiver | Giora Biran, Matthew Adam Cushing, Allen James Gavin, Mark E. Kautzman, Jamie R. Kuesel +8 more | 2007-06-19 |
| 6895482 | Reordering and flushing commands in a computer memory subsystem | Herman L. Blackmon, Kent Harold Haselhorst, James Anthony Marcella | 2005-05-17 |
| 6836831 | Independent sequencers in a DRAM control structure | John Michael Borkenhagen, Brian T. Vanderpool | 2004-12-28 |
| 6684279 | Method, apparatus, and computer program product for controlling data transfer | Robert Kruse | 2004-01-27 |
| 6628662 | Method and system for multilevel arbitration in a non-blocking crossbar switch | Herman L. Blackmon, Kent Harold Haselhorst, James Anthony Marcella | 2003-09-30 |
| 6557069 | Processor-memory bus architecture for supporting multiple processors | Kent Harold Haselhorst, Russell D. Hoover, James Anthony Marcella, George Wayne Nation | 2003-04-29 |
| 6526469 | Bus architecture employing varying width uni-directional command bus | Kent Harold Haselhorst, Russell D. Hoover, James Anthony Marcella | 2003-02-25 |
| 6523080 | Shared bus non-sequential data ordering method and apparatus | Herman L. Blackmon, Lyle Edwin Grosbach, Kent Harold Haselhorst, David J. Krolak, James Anthony Marcella +1 more | 2003-02-18 |
| 6513091 | Data routing using status-response signals | Herman L. Blackmon, Kent Harold Haselhorst, James Anthony Marcella | 2003-01-28 |
| 6505306 | Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initialization | Herman L. Blackmon, Kent Harold Haselhorst, James Anthony Marcella | 2003-01-07 |
| 6295591 | Method of upgrading and/or servicing memory without interrupting the operation of the system | Richard Bealkowski, Scott Douglas Clark, Sudhir Dhawan | 2001-09-25 |