Issued Patents All Time
Showing 51–75 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9256428 | Load latency speculation in an out-of-order computer processor | Timothy H. Heil, Andrew D. Hilton | 2016-02-09 |
| 9251116 | Direct interthread communication dataport pack/unpack and load/save | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-02-02 |
| 9223753 | Dynamic range adjusting floating point execution unit | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2015-12-29 |
| 9218039 | Chip level power reduction using encoded communications | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-12-22 |
| 9195463 | Processing core with speculative register preprocessing in unused execution unit cycles | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2015-11-24 |
| 9189051 | Power reduction by minimizing bit transitions in the hamming distances of encoded communications | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-11-17 |
| 9183399 | Instruction set architecture with secure clear instructions for protecting processing unit architected state information | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-11-10 |
| 9170954 | Translation management instructions for updating address translation data structures in remote processing nodes | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-10-27 |
| 9147078 | Instruction set architecture with secure clear instructions for protecting processing unit architected state information | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-09-29 |
| 9092256 | Vector execution unit with prenormalization of denormal values | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-07-28 |
| 9092257 | Vector execution unit with prenormalization of denormal values | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-07-28 |
| 9081501 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +55 more | 2015-07-14 |
| 9075599 | Opcode space minimizing architecture utilizing a least significant portion of an instruction address as upper register address bits | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2015-07-07 |
| 9053049 | Translation management instructions for updating address translation data structures in remote processing nodes | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-06-09 |
| 9032191 | Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-05-12 |
| 9021004 | Execution unit with inline pseudorandom number generator | Matthew R. Tubbs | 2015-04-28 |
| 8984260 | Predecode logic autovectorizing a group of scalar instructions including result summing add instruction to a vector instruction for execution in vector unit with dot product adder | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-03-17 |
| 8954755 | Memory address translation-based data encryption with integrated encryption engine | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-02-10 |
| 8935694 | System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2015-01-13 |
| 8930432 | Floating point execution unit with fixed point functionality | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2015-01-06 |
| 8892851 | Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2014-11-18 |
| 8880852 | Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2014-11-04 |
| 8751830 | Memory address translation-based data encryption/compression | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2014-06-10 |
| 8707094 | Fault tolerant stability critical execution checking using redundant execution pipelines | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2014-04-22 |
| 8629867 | Performing vector multiplication | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2014-01-14 |