Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10672368 | No miss cache structure for real-time image transformations with multiple LSR processing engines | Ryan Scott Haraden, Adam J. Muff, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung +1 more | 2020-06-02 |
| 10514753 | Selectively applying reprojection processing to multi-layer scenes for optimizing late stage reprojection power | Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Adam J. Muff, Gene Leung | 2019-12-24 |
| 10410349 | Selective application of reprojection processing on layer sub-regions for optimizing late stage reprojection power | Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Adam J. Muff, Gene Leung | 2019-09-10 |
| 10403029 | Methods and systems for multistage post-rendering image transformation | Miguel Comparan, Ryan Scott Haraden, Jeffrey Powers Bradford | 2019-09-03 |
| 10360832 | Post-rendering image transformation using parallel image transformation pipelines | Miguel Comparan, Christopher Jon Johnson, Jeffrey Powers Bradford | 2019-07-23 |
| 10338816 | Reducing negative effects of insufficient data throughput for real-time processing | Ishan Jitendra Bhatt, Miguel Comparan, Ryan Scott Haraden, Jeffrey Powers Bradford, Gene Leung | 2019-07-02 |
| 10255891 | No miss cache structure for real-time image transformations with multiple LSR processing engines | Ryan Scott Haraden, Adam J. Muff, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung +1 more | 2019-04-09 |
| 10242654 | No miss cache structure for real-time image transformations | Jeffrey Powers Bradford, Miguel Comparan, Gene Leung, Adam J. Muff, Ryan Scott Haraden +1 more | 2019-03-26 |
| 10241470 | No miss cache structure for real-time image transformations with data compression | Gene Leung, Jeffrey Powers Bradford, Adam J. Muff, Miguel Comparan, Ryan Scott Haraden +1 more | 2019-03-26 |
| 10095408 | Reducing negative effects of insufficient data throughput for real-time processing | Ishan Jitendra Bhatt, Miguel Comparan, Ryan Scott Haraden, Jeffrey Powers Bradford, Gene Leung | 2018-10-09 |
| 9978118 | No miss cache structure for real-time image transformations with data compression | Gene Leung, Jeffrey Powers Bradford, Adam J. Muff, Miguel Comparan, Ryan Scott Haraden +1 more | 2018-05-22 |
| 9747225 | Interrupt controller | Robert A. Shearer, Elene Terry, Jonathan Ross | 2017-08-29 |
| 8219745 | Memory controller to utilize DRAM write buffers | Mark David Bellows, Kent Harold Haselhorst, Ryan Abel Heakendorf, Paul Allen Ganfield | 2012-07-10 |
| 8213428 | Methods and apparatus for indexing memory of a network processor | Gerald G. Fagerness, Kerry Christopher Imming, Brian M. McKevett, James Francis Mikos | 2012-07-03 |
| 8170024 | Implementing pointer and stake model for frame alteration code in a network processor | Kerry Christopher Imming, John D. Irish, Joseph Franklin Logan, Michael S. Siegel | 2012-05-01 |
| 7925823 | Reuse of functional data buffers for pattern buffers in XDR DRAM | Mark David Bellows, Kent Harold Haselhorst, Paul Allen Ganfield | 2011-04-12 |
| 7761682 | Memory controller operating in a system with a variable system clock | Melissa Ann Barnum, Mark David Bellows, Paul Allen Ganfield, Lonny Lambrecht | 2010-07-20 |
| 7757040 | Memory command and address conversion between an XDR interface and a double data rate interface | Mark David Bellows, John D. Irish, David Alan Norgaard | 2010-07-13 |
| 7757006 | Implementing conditional packet alterations based on transmit port | Kerry Christopher Imming, John D. Irish, Andrew Henry Wottreng | 2010-07-13 |
| 7752379 | Managing write-to-read turnarounds in an early read after write memory system | Mark David Bellows, Paul Allen Ganfield, Kent Harold Haselhorst, Ryan Abel Heckendorf | 2010-07-06 |
| 7669028 | Optimizing data bandwidth across a variable asynchronous clock domain | Mark David Bellows, Brian M. McKevett | 2010-02-23 |
| 7487318 | Managing write-to-read turnarounds in an early read after write memory system | Mark David Bellows, Paul Allen Ganfield, Kent Harold Haselhorst, Ryan Abel Heckendorf | 2009-02-03 |
| 7475161 | Implementing conditional packet alterations based on transmit port | Kerry Christopher Imming, John D. Irish, Andrew Henry Wottreng | 2009-01-06 |
| 7467277 | Memory controller operating in a system with a variable system clock | Melissa Ann Barnum, Mark David Bellows, Paul Allen Ganfield, Lonny Lambrecht | 2008-12-16 |
| 7380052 | Reuse of functional data buffers for pattern buffers in XDR DRAM | Mark David Bellows, Kent Harold Haselhorst, Paul Allen Ganfield | 2008-05-27 |