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Implementing lane shuffle for fault-tolerant communication links |
Kerry Christopher Imming, John D. Irish, Ibrahim Abdel-Rahman Ouda |
2014-07-29 |
| 8493842 |
Implementing exchange of failing lane information for fault-tolerant communication links |
Kerry Christopher Imming |
2013-07-23 |
| 7752379 |
Managing write-to-read turnarounds in an early read after write memory system |
Mark David Bellows, Paul Allen Ganfield, Kent Harold Haselhorst, Tolga Ozguner |
2010-07-06 |
| 7613873 |
Deferring refreshes during calibrations in memory systems |
Mark David Bellows |
2009-11-03 |
| 7558908 |
Structure of sequencers that perform initial and periodic calibrations in a memory system |
Mark David Bellows |
2009-07-07 |
| 7490204 |
Using constraints to simplify a memory controller |
Mark David Bellows |
2009-02-10 |
| 7487318 |
Managing write-to-read turnarounds in an early read after write memory system |
Mark David Bellows, Paul Allen Ganfield, Kent Harold Haselhorst, Tolga Ozguner |
2009-02-03 |
| 7380083 |
Memory controller capable of locating an open command cycle to issue a precharge packet |
Mark David Bellows |
2008-05-27 |
| 7356642 |
Deferring refreshes during calibrations in memory systems |
Mark David Bellows |
2008-04-08 |
| 7321961 |
Method and apparatus to avoid collisions between row activate and column read or column write commands |
Mark David Bellows |
2008-01-22 |
| 7321950 |
Method and apparatus for managing write-to-read turnarounds in an early read after write memory system |
Mark David Bellows, Paul Allen Ganfield, Kent Harold Haselhorst, Tolga Ozguner |
2008-01-22 |
| 7305517 |
Structure of sequencers that perform initial and periodic calibrations in a memory system |
Mark David Bellows |
2007-12-04 |
| 7272699 |
Flexible sub-column to sub-row mapping for sub-page activation in XDR™ DRAMs |
Paul Allen Ganfield |
2007-09-18 |