Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8645667 | Operating system management of address-translation-related data structures and hardware lookasides | Bradly G. Frey, Michal Ostrowski | 2014-02-04 |
| 8589630 | Methods and apparatus for handling a cache miss | John D. Irish, Chad B. McBride | 2013-11-19 |
| 8589657 | Operating system management of address-translation-related data structures and hardware lookasides | Bradly G. Frey, Michal Ostrowski | 2013-11-19 |
| 8327075 | Methods and apparatus for handling a cache miss | John D. Irish, Chad B. McBride | 2012-12-04 |
| 8296547 | Loading entries into a TLB in hardware via indirect TLB entries | Timothy H. Heil, Benjamin Herrenschmidt, Jon K. Kriegel, Paul Mackerras | 2012-10-23 |
| 8180941 | Mechanisms for priority control in resource allocation | Wen-Tzer T. Chen, Charles Ray Johns, Ram Raghavan | 2012-05-15 |
| 8127082 | Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations | Chad B. McBride, John D. Irish | 2012-02-28 |
| 8108617 | Method to bypass cache levels in a cache coherent system | Timothy H. Heil, James Allen Rose | 2012-01-31 |
| 8103835 | Low-cost cache coherency for accelerators | Scott Douglas Clark | 2012-01-24 |
| 8028118 | Using an index value located on a page table to index page attributes | Timothy H. Heil, James Allen Rose | 2011-09-27 |
| 7827343 | Method and apparatus for providing accelerator support in a bus protocol | Bradly G. Frey, Steven M. Thurber | 2010-11-02 |
| 7814279 | Low-cost cache coherency for accelerators | Scott Douglas Clark | 2010-10-12 |
| 7757006 | Implementing conditional packet alterations based on transmit port | Kerry Christopher Imming, John D. Irish, Tolga Ozguner | 2010-07-13 |
| 7721023 | I/O address translation method for specifying a relaxed ordering for I/O accesses | John D. Irish, Charles Ray Johns | 2010-05-18 |
| 7716423 | Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes | John D. Irish, Chad B. McBride | 2010-05-11 |
| 7631131 | Priority control in resource allocation for low request rate, latency-sensitive units | Wen-Tzer T. Chen, Charles Ray Johns, Ram Raghavan | 2009-12-08 |
| 7552269 | Synchronizing a plurality of processors | Steven M. Thurber | 2009-06-23 |
| 7539840 | Handling concurrent address translation cache misses and hits under those misses while maintaining command order | John D. Irish, Chad B. McBride, Ibrahim Abdel-Rahman Ouda | 2009-05-26 |
| 7530068 | Method of resource allocation using an access control mechanism | Scott Douglas Clark, Michael Norman Day, Charles Ray Johns | 2009-05-05 |
| 7475161 | Implementing conditional packet alterations based on transmit port | Kerry Christopher Imming, John D. Irish, Tolga Ozguner | 2009-01-06 |
| 7472227 | Invalidating multiple address cache entries | Chad B. McBride | 2008-12-30 |
| 6880113 | Conditional hardware scan dump data capture | Gary D. Anderson, Stephanie Maria Forsman, Alongkorn Kitamorn, Michael Youhour Lim | 2005-04-12 |
| 6697935 | Method and apparatus for selecting thread switch events in a multithreaded processor | John Michael Borkenhagen, Richard J. Eickemeyer, William T. Flynn | 2004-02-24 |
| 6567839 | Thread switch control in a multithreaded processor system | John Michael Borkenhagen, Richard J. Eickemeyer, William T. Flynn, Sheldon B. Levenstein | 2003-05-20 |
| 6334167 | System and method for memory self-timed refresh for reduced power consumption | Edward T. Gerchman, Mark C. Gildea, William Paul Hovis, Randall S. Jensen, Warren E. Maule +1 more | 2001-12-25 |