Issued Patents All Time
Showing 51–75 of 189 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9317291 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-04-19 |
| 9311096 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-04-12 |
| 9311090 | Indirect instruction predication | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-04-12 |
| 9304771 | Indirect instruction predication | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-04-05 |
| 9292965 | Accelerated data structure positioning based upon view orientation | David Keith Fowler, Eric O. Mejdrich, Paul E. Schardt | 2016-03-22 |
| 9292290 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-03-22 |
| 9286071 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-03-15 |
| 9274591 | General purpose processing unit with low power digital signal processing (DSP) mode | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-03-01 |
| 9256574 | Dynamic thread status retrieval using inter-thread communication | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2016-02-09 |
| 9256573 | Dynamic thread status retrieval using inter-thread communication | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2016-02-09 |
| 9251116 | Direct interthread communication dataport pack/unpack and load/save | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-02-02 |
| 9244840 | Cache swizzle with inline transposition | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2016-01-26 |
| 9239791 | Cache swizzle with inline transposition | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2016-01-19 |
| 9218039 | Chip level power reduction using encoded communications | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2015-12-22 |
| 9195443 | Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2015-11-24 |
| 9189051 | Power reduction by minimizing bit transitions in the hamming distances of encoded communications | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2015-11-17 |
| 9183399 | Instruction set architecture with secure clear instructions for protecting processing unit architected state information | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2015-11-10 |
| 9176885 | Combined cache inject and lock operation | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2015-11-03 |
| 9170954 | Translation management instructions for updating address translation data structures in remote processing nodes | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2015-10-27 |
| 9147078 | Instruction set architecture with secure clear instructions for protecting processing unit architected state information | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2015-09-29 |
| 9134778 | Power distribution management in a system on a chip | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2015-09-15 |
| 9134779 | Power distribution management in a system on a chip | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2015-09-15 |
| 9122465 | Programmable microcode unit for mapping plural instances of an instruction in plural concurrently executed instruction streams to plural microcode sequences in plural memory partitions | Paul E. Schardt, Matthew R. Tubbs | 2015-09-01 |
| 9092347 | Allocating cache for use as a dedicated local storage | Miguel Comparan, Russell D. Hoover, Alfred T. Watson, III | 2015-07-28 |
| 9092257 | Vector execution unit with prenormalization of denormal values | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2015-07-28 |