Issued Patents All Time
Showing 51–75 of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9092256 | Vector execution unit with prenormalization of denormal values | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2015-07-28 |
| 9075599 | Opcode space minimizing architecture utilizing a least significant portion of an instruction address as upper register address bits | Mark J. Hickey, Adam J. Muff, Charles D. Wait | 2015-07-07 |
| 9053049 | Translation management instructions for updating address translation data structures in remote processing nodes | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2015-06-09 |
| 9032191 | Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2015-05-12 |
| 9021004 | Execution unit with inline pseudorandom number generator | Adam J. Muff | 2015-04-28 |
| 8984260 | Predecode logic autovectorizing a group of scalar instructions including result summing add instruction to a vector instruction for execution in vector unit with dot product adder | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2015-03-17 |
| 8954755 | Memory address translation-based data encryption with integrated encryption engine | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2015-02-10 |
| 8935694 | System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2015-01-13 |
| 8930432 | Floating point execution unit with fixed point functionality | Mark J. Hickey, Adam J. Muff, Charles D. Wait | 2015-01-06 |
| 8892851 | Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2014-11-18 |
| 8880852 | Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address | Mark J. Hickey, Adam J. Muff, Charles D. Wait | 2014-11-04 |
| 8836709 | Vector register file caching of context data structure for maintaining state data in a multithreaded image processing pipeline | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2014-09-16 |
| 8751830 | Memory address translation-based data encryption/compression | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2014-06-10 |
| 8719455 | DMA-based acceleration of command push buffer between host and target devices | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2014-05-06 |
| 8711163 | Reuse of static image data from prior image frames to reduce rasterization requirements | Paul E. Schardt, Robert A. Shearer, Eric O. Mejdrich | 2014-04-29 |
| 8707094 | Fault tolerant stability critical execution checking using redundant execution pipelines | Mark J. Hickey, Adam J. Muff, Charles D. Wait | 2014-04-22 |
| 8692825 | Parallelized streaming accelerated data structure generation | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2014-04-08 |
| 8661455 | Performance event triggering through direct interthread communication on a network on chip | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2014-02-25 |
| 8629867 | Performing vector multiplication | Mark J. Hickey, Adam J. Muff, Charles D. Wait | 2014-01-14 |
| 8627329 | Multithreaded physics engine with predictive load balancing | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2014-01-07 |
| 8619078 | Parallelized ray tracing | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2013-12-31 |
| 8593459 | Tree insertion depth adjustment based on view frustum and distance culling | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2013-11-26 |
| 8587596 | Multithreaded software rendering pipeline with dynamic performance-based reallocation of raster threads | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2013-11-19 |
| 8587594 | Allocating resources based on a performance statistic | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2013-11-19 |
| 8549262 | Instruction operand addressing using register address sequence detection | Eric O. Mejdrich, Adam J. Muff, Robert A. Shearer | 2013-10-01 |