Issued Patents All Time
Showing 101–124 of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8108908 | Security methodology to prevent user from compromising throughput in a highly threaded network on a chip processor | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2012-01-31 |
| 8102884 | Direct inter-thread communication buffer that supports software controlled arbitrary vector operand selection in a densely threaded network on a chip | Adam J. Muff, Robert A. Shearer | 2012-01-24 |
| 8090756 | Method and apparatus for generating trigonometric results | — | 2012-01-03 |
| 8028153 | Data dependent instruction decode | Mark J. Hickey, Adam J. Muff, Charles D. Wait | 2011-09-27 |
| 8024616 | Pseudo random process state register for fast random process test generation | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2011-09-20 |
| 7992043 | Software debugger for packets in a network on a chip | Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer | 2011-08-02 |
| 7975172 | Redundant execution of instructions in multistage execution pipeline during unused execution cycles | Mark J. Hickey, Adam J. Muff, Charles D. Wait | 2011-07-05 |
| 7945764 | Processing unit incorporating multirate execution unit | Eric O. Mejdrich, Adam J. Muff | 2011-05-17 |
| 7941644 | Simultaneous multi-thread instructions issue to execution units while substitute injecting sequence of instructions for long latency sequencer instruction via multiplexer | Eric O. Mejdrich, Adam J. Muff | 2011-05-10 |
| 7926009 | Dual independent and shared resource vector execution units with shared register file | Eric O. Mejdrich, Adam J. Muff | 2011-04-12 |
| 7921278 | Early exit processing of iterative refinement algorithm using register dependency disable | Adam J. Muff | 2011-04-05 |
| 7913066 | Early exit processing of iterative refinement algorithm using register dependency disable and programmable early exit condition | Adam J. Muff | 2011-03-22 |
| 7904699 | Processing unit incorporating instruction-based persistent vector multiplexer control | Eric O. Mejdrich, Adam J. Muff, Robert A. Shearer | 2011-03-08 |
| 7904700 | Processing unit incorporating special purpose register for use with instruction-based persistent vector multiplexer control | Eric O. Mejdrich, Adam J. Muff, Robert A. Shearer | 2011-03-08 |
| 7873066 | Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip | Adam J. Muff, Robert A. Shearer | 2011-01-18 |
| 7873816 | Pre-loading context states by inactive hardware thread in advance of context switch | Mark J. Hickey, Stephen Joseph Schwinn, Charles D. Wait | 2011-01-18 |
| 7868894 | Operand multiplexor control modifier instruction in a fine grain multithreaded vector microprocessor | Eric O. Mejdrich, Adam J. Muff | 2011-01-11 |
| 7814299 | Designating operands with fewer bits in instruction code by indexing into destination register history table for each thread | Mark J. Hickey, Adam J. Muff, Charles D. Wait | 2010-10-12 |
| 7814303 | Execution of a sequence of vector instructions preceded by a swizzle sequence instruction specifying data element shuffle orders respectively | Adam J. Muff, Robert A. Shearer | 2010-10-12 |
| 7809925 | Processing unit incorporating vectorizable execution unit | Eric O. Mejdrich, Adam J. Muff | 2010-10-05 |
| 7634527 | Reciprocal estimate computation methods and apparatus | Sherman M. Dance, Andrew Patrick Freemyer | 2009-12-15 |
| 7542044 | Optimized specular highlight generation | Gordon Clyde Fossum, Stephen Joseph Schwinn | 2009-06-02 |
| 7456837 | Optimized specular highlight generation | Gordon Clyde Fossum, Stephen Joseph Schwinn | 2008-11-25 |
| 7143126 | Method and apparatus for implementing power of two floating point estimation | Gordon Clyde Fossum, Stephen Joseph Schwinn | 2006-11-28 |