Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6622236 | Microprocessor instruction fetch unit for processing instruction groups having multiple branch instructions | Brian R. Konigsburg, Dave S. Levitan | 2003-09-16 |
| 6332181 | Recovery mechanism for L1 data cache parity errors | Douglas Craig Bossen, Namratha Jaisimha, Avijit Saha | 2001-12-18 |
| 6148394 | Apparatus and method for tracking out of order load instructions to avoid data coherency violations in a processor | Shih-Hsiung S. Tung, David Scott Ray, Barry Duane Williamson | 2000-11-14 |
| 6061785 | Data processing system having an apparatus for out-of-order register operations and method therefor | A. James Van Norstrand, Jr., David A. Schroter | 2000-05-09 |
| 6035394 | System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel | David Scott Ray, David A. Schroter, A. James Van Norstrand, Jr., Barry Duane Williamson | 2000-03-07 |
| 5860150 | Instruction pre-fetching of a cache line within a processor | Michael John Mayfield, Era K. Nangia, Milford John Peterson | 1999-01-12 |
| 5721864 | Prefetching instructions between caches | Michael John Mayfield, Era K. Nangia, Milford John Peterson | 1998-02-24 |
| 5390312 | Access look-aside facility | Robert M. Dinkjian, Theodore J. Schmitt | 1995-02-14 |
| 5319761 | Directory look-aside table for a virtual storage system including means for minimizing synonym entries | Richard J. Schmalz, Theodore J. Schmitt, Arnold S. Tran, Shih-Hsiung S. Tung | 1994-06-07 |