Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11907542 | Virtualized-in-hardware input output memory management | Sanjay Patel | 2024-02-20 |
| 11599270 | Virtualized-in-hardware input output memory management | Sanjay Patel | 2023-03-07 |
| 10671391 | Modeless instruction execution with 64/32-bit addressing | Ranganathan Sudhakar | 2020-06-02 |
| 10649773 | Processors supporting atomic writes to multiword memory locations and methods | Andrew F. Glew, Sanjay Patel, James Hippisley Robinson, Sudhakar Ranganathan | 2020-05-12 |
| 10642501 | Hardware virtualized input output memory management unit | Sanjay Patel | 2020-05-05 |
| 10185665 | Translation lookaside buffer | Sanjay Patel | 2019-01-22 |
| 10162659 | Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions | Sanjay Patel | 2018-12-25 |
| 10108548 | Processors and methods for cache sparing stores | Era K. Nangia, Debasish Chandra, Ranganathan Sudhakar | 2018-10-23 |
| 9830275 | Translation lookaside buffer | Sanjay Patel | 2017-11-28 |
| 9740454 | Crossing pipelined data between circuitry in different clock domains | — | 2017-08-22 |
| 9740557 | Pipelined ECC-protected memory access | Ranganathan Sudhakar | 2017-08-22 |
| 9367286 | Crossing pipelined data between circuitry in different clock domains | — | 2016-06-14 |
| 9223721 | Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions | Sanjay Patel | 2015-12-29 |
| 9086906 | Apparatus and method for guest and root register sharing in a virtual machine | Sanjay Patel | 2015-07-21 |
| 8897316 | On-chip packet cut-through | Edmund CHEN, Ramanathan Lakshmikanthan, Brian Alleyne, Stephen Chow, Patrick Wang +4 more | 2014-11-25 |
| 8700874 | Digital counter segmented into short and long access time memory | Edmund Chen, Brian Alleyne, Robert Hathaway, Todd David Basso | 2014-04-15 |
| 7986706 | Hierarchical pipelined distributed scheduling traffic manager | Thomas C. Yip, Michael Feng, Sun Den Chen, Stephen Chow, Edward Ho +3 more | 2011-07-26 |
| 7352748 | Updating of routing data in a network element | Gary S. Delp | 2008-04-01 |
| 7254651 | Scheduler for a direct memory access device having multiple channels | Ravikrishna Cherukuri | 2007-08-07 |
| 7206310 | Method and apparatus for replicating packet data with a network element | Edmund Chen, Ravikrishna Cherukuri | 2007-04-17 |
| 6961822 | Free memory manager scheme and cache | Ravikrishna Cherukuri | 2005-11-01 |
| 6618793 | Free memory manager scheme and cache | Ravikrishna Cherukuri | 2003-09-09 |
| 6345328 | Gear box for multiple clock domains | Sridhar Subramanian, Ravikrishna Cherukuri | 2002-02-05 |
| 6253262 | Arbitrating FIFO implementation which positions input request in a buffer according to its status | Scott Waldron, Ravikrishna Cherukuri | 2001-06-26 |
| 6173378 | Method for ordering a request for access to a system memory using a reordering buffer or FIFO | Sridhar Subramanian, Ravikrishna Cherukuri | 2001-01-09 |