Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7254651 | Scheduler for a direct memory access device having multiple channels | Ranjit J. Rozario | 2007-08-07 |
| 7206310 | Method and apparatus for replicating packet data with a network element | Edmund Chen, Ranjit J. Rozario | 2007-04-17 |
| 7020736 | Method and apparatus for sharing memory space across mutliple processing units | — | 2006-03-28 |
| 7007095 | Method and apparatus for unscheduled flow control in packet form | Edmund Chen, Ruchi Wadhawan | 2006-02-28 |
| 6976096 | Method and apparatus for controlling the admission of data into a network element | Gregory G. Minshall | 2005-12-13 |
| 6961822 | Free memory manager scheme and cache | Ranjit J. Rozario | 2005-11-01 |
| 6618793 | Free memory manager scheme and cache | Ranjit J. Rozario | 2003-09-09 |
| 6397238 | Method and apparatus for rounding in a multiplier | Stuart F. Oberman, Norbert Juffa, Ming Siu, Frederick Daniel Weber | 2002-05-28 |
| 6381625 | Method and apparatus for calculating a power of an operand | Stuart F. Oberman, Norbert Juffa, Ming Siu, Frederick Daniel Weber | 2002-04-30 |
| 6345328 | Gear box for multiple clock domains | Ranjit J. Rozario, Sridhar Subramanian | 2002-02-05 |
| 6253262 | Arbitrating FIFO implementation which positions input request in a buffer according to its status | Ranjit J. Rozario, Scott Waldron | 2001-06-26 |
| 6223198 | Method and apparatus for multi-function arithmetic | Stuart F. Oberman, Norbert Juffa, Ming Siu, Frederick Daniel Weber | 2001-04-24 |
| 6173378 | Method for ordering a request for access to a system memory using a reordering buffer or FIFO | Ranjit J. Rozario, Sridhar Subramanian | 2001-01-09 |
| 6026483 | Method and apparatus for simultaneously performing arithmetic on two or more pairs of operands | Stuart F. Oberman, Ming Siu | 2000-02-15 |
| 6006307 | Computer system employing a mirrored memory system for providing prefetch bandwidth | — | 1999-12-21 |
| 5745732 | Computer system including system controller with a write buffer and plural read buffers for decoupled busses | Ranjit J. Rozario | 1998-04-28 |