Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9761202 | Seamless video transitions | Christopher P. Tann | 2017-09-12 |
| 9262353 | Interrupt distribution scheme | Josh P. de Cesare, Erik P. Machnicki, Mark D. Hayter | 2016-02-16 |
| 8959270 | Interrupt distribution scheme | Josh P. de Cesare, Erik P. Machnicki, Mark D. Hayter | 2015-02-17 |
| 8762653 | Dynamic QoS upgrading | Sukalpa Biswas, Hao Chen | 2014-06-24 |
| 8631213 | Dynamic QoS upgrading | Sukalpa Biswas, Hao Chen | 2014-01-14 |
| 8578079 | Power managed lock optimization | Josh P. de Cesare, Michael J. Smith, Puneet Kumar, Bernard J. Semeria | 2013-11-05 |
| 8566485 | Data transformation during direct memory access | Dominic Go, Mark D. Hayter, Zongjian Chen | 2013-10-22 |
| 8417844 | DMA controller which performs DMA assist for one peripheral interface controller and DMA operation for another peripheral interface controller | Dominic Go, Mark D. Hayter, Zongjian Chen | 2013-04-09 |
| 8332559 | Power managed lock optimization | Josh P. de Cesare, Michael J. Smith, Puneet Kumar, Bernard J. Semeria | 2012-12-11 |
| 8209446 | DMA controller that passes destination pointers from transmit logic through a loopback buffer to receive logic to write data to memory | Dominic Go, Mark D. Hayter, Zongjian Chen | 2012-06-26 |
| 8176257 | Cache used both as cache and staging buffer | Jason M. Kassoff, George Kong Yiu | 2012-05-08 |
| 8156275 | Power managed lock optimization | Josh P. de Cesare, Michael J. Smith, Puneet Kumar, Bernard J. Semeria | 2012-04-10 |
| 8032670 | Method and apparatus for generating DMA transfers to memory | Dominic Go, Mark D. Hayter, Zongjian Chen | 2011-10-04 |
| 7970970 | Non-blocking address switch with shallow per agent queues | Sridhar Subramanian, James B. Keller, George Kong Yiu, Ramesh Gunna | 2011-06-28 |
| 7949829 | Cache used both as cache and staging buffer | Jason M. Kassoff, George Kong Yiu | 2011-05-24 |
| 7808999 | Method and apparatus for out-of-order processing of packets using linked lists | Edmund Chen, John G. Favor, Gregory G. Minshall | 2010-10-05 |
| 7752366 | Non-blocking address switch with shallow per agent queues | Sridhar Subramanian, James B. Keller, George Kong Yiu, Ramesh Gunna | 2010-07-06 |
| 7698478 | Managed credit update | James Wang, Choon Ping Chng, Mark D. Hayter | 2010-04-13 |
| 7680963 | DMA controller configured to process control descriptors and transfer descriptors | Dominic Go, Mark D. Hayter, Zongjian Chen | 2010-03-16 |
| 7624235 | Cache used both as cache and staging buffer | Jason M. Kassoff, George Kong Yiu | 2009-11-24 |
| 7512129 | Method and apparatus for implementing a switching unit including a bypass path | John G. Favor, Edmund Chen | 2009-03-31 |
| 7496695 | Unified DMA | Dominic Go, Mark D. Hayter, Zongjian Chen | 2009-02-24 |
| 7461190 | Non-blocking address switch with shallow per agent queues | Sridhar Subramanian, James B. Keller, George Kong Yiu, Ramesh Gunna | 2008-12-02 |
| 7426601 | Segmented interconnect for connecting multiple agents in a system | Sridhar Subramanian, James B. Keller, George Kong Yiu | 2008-09-16 |
| 7349399 | Method and apparatus for out-of-order processing of packets using linked lists | Edmund Chen, John G. Favor, Gregory G. Minshall | 2008-03-25 |