Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7900076 | Power management method for a pipelined computer system | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2011-03-01 |
| 7900075 | Pipelined computer system with power management control | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2011-03-01 |
| 7509512 | Instruction-initiated method for suspending operation of a pipelined data processor | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2009-03-24 |
| 7120810 | Instruction-initiated power management method for a pipelined data processor | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2006-10-10 |
| 7062666 | Signal-initiated method for suspending operation of a pipelined data processor | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2006-06-13 |
| 7000132 | Signal-initiated power management method for a pipelined data processor | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2006-02-14 |
| 6978390 | Pipelined data processor with instruction-initiated power management control | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2005-12-20 |
| 6910141 | Pipelined data processor with signal-initiated power management control | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2005-06-21 |
| 6721894 | METHOD FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE CONDITIONS ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2004-04-13 |
| 6694443 | SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE TO CONDITION ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2004-02-17 |
| 6343363 | Method of invoking a low power mode in a computer system using a halt instruction | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2002-01-29 |
| 6205560 | Debug system allowing programmable selection of alternate debug mechanisms such as debug handler, SMI, or JTAG | Mark W. Hervin, Stanley D. Harder, William C. Patton, JR. | 2001-03-20 |
| 6138230 | Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline | Mark W. Hervin, Steven C. McMahan, Raul A. Garibay, Jr. | 2000-10-24 |
| 6088807 | Computer system with low power mode invoked by halt instruction | Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin | 2000-07-11 |
| 6073231 | Pipelined processor with microcontrol of register translation hardware | Mark W. Hervin | 2000-06-06 |
| 5963984 | Address translation unit employing programmable page size | Raul A. Garibay, Jr., Marc A. Quattromani, Douglas R. Beard | 1999-10-05 |
| 5937178 | Register file for registers with multiple addressable sizes using read-modify-write for register file update | — | 1999-08-10 |
| 5907860 | System and method of retiring store data from a write buffer | Raul A. Garibay, Jr., Marc A. Quattromani | 1999-05-25 |
| 5898815 | I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency | Marvin W. Martinez, Jr. | 1999-04-27 |
| 5860111 | Coherency for write-back cache in a system designed for write-through cache including export-on-hold | Marvin W. Martinez, Jr., Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko, Raul A. Garibay, Jr. +1 more | 1999-01-12 |
| 5838897 | Debugging a processor using data output during idle bus cycles | Mark W. Hervin | 1998-11-17 |
| 5784589 | Distributed free register tracking for register renaming using an availability tracking register associated with each stage of an execution pipeline | — | 1998-07-21 |
| 5771365 | Condensed microaddress generation in a complex instruction set computer | Steven C. McMahan | 1998-06-23 |
| 5664149 | Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol | Marvin W. Martinez, Jr., Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko, Raul A. Garibay, Jr. +1 more | 1997-09-02 |
| 5644741 | Processor with single clock decode architecture employing single microROM | Mark W. Hervin, Steven C. McMahan, Raul A. Garibay, Jr. | 1997-07-01 |