| 6408002 |
Torus routing element error handling and self-clearing with missing or extraneous control code feature |
Jeffery L. Moll, Mark S. Myers |
2002-06-18 |
| 6219773 |
System and method of retiring misaligned write operands from a write buffer |
Raul A. Garibay, Jr. |
2001-04-17 |
| 6026444 |
TORUS routing element error handling and self-clearing with link lockup prevention |
Jeffery L. Moll, Mark S. Myers |
2000-02-15 |
| 6016510 |
TORUS routing element error handling and self-clearing with programmable watermarking |
Mark S. Myers |
2000-01-18 |
| 5963984 |
Address translation unit employing programmable page size |
Raul A. Garibay, Jr., Douglas R. Beard, Mark Bluhm |
1999-10-05 |
| 5907860 |
System and method of retiring store data from a write buffer |
Raul A. Garibay, Jr., Mark Bluhm |
1999-05-25 |
| 5835949 |
Method of identifying and self-modifying code |
Raul A. Garibay, Jr., Steven C. McMahan, Mark W. Hervin |
1998-11-10 |
| 5752274 |
Address translation unit employing a victim TLB |
Raul A. Garibay, Jr., Douglas R. Beard |
1998-05-12 |
| 5740398 |
Program order sequencing of data in a microprocessor with write buffer |
Nital Patwa |
1998-04-14 |
| 5615402 |
Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch |
Raul A. Garibay, Jr. |
1997-03-25 |
| 5596740 |
Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks |
John K. Eitrheim |
1997-01-21 |
| 5584009 |
System and method of retiring store data from a write buffer |
Raul A. Garibay, Jr., Mark Bluhm |
1996-12-10 |
| 5471598 |
Data dependency detection and handling in a microprocessor with write buffer |
Raul A. Garibay, Jr., Nital Patwa, Mark W. Hervin |
1995-11-28 |
| 5291498 |
Error detecting method and apparatus for computer memory having multi-bit output memory circuits |
James A. Jackson, Sr., Kevin M. Lowderman |
1994-03-01 |