Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5963984 | Address translation unit employing programmable page size | Marc A. Quattromani, Douglas R. Beard, Mark Bluhm | 1999-10-05 |
| 5907860 | System and method of retiring store data from a write buffer | Marc A. Quattromani, Mark Bluhm | 1999-05-25 |
| 5860111 | Coherency for write-back cache in a system designed for write-through cache including export-on-hold | Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko +1 more | 1999-01-12 |
| 5835949 | Method of identifying and self-modifying code | Marc A. Quattromani, Steven C. McMahan, Mark W. Hervin | 1998-11-10 |
| 5805879 | In a pipelined processor, setting a segment access indicator during execution stage using exception handling | Mark W. Hervin | 1998-09-08 |
| 5752274 | Address translation unit employing a victim TLB | Marc A. Quattromani, Douglas R. Beard | 1998-05-12 |
| 5664149 | Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol | Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko +1 more | 1997-09-02 |
| 5644741 | Processor with single clock decode architecture employing single microROM | Mark Bluhm, Mark W. Hervin, Steven C. McMahan | 1997-07-01 |
| 5632037 | Microprocessor having power management circuitry with coprocessor support | Robert Maher, Margaret R. Herubin, Mark Bluhm | 1997-05-20 |
| 5630143 | Microprocessor with externally controllable power management | Robert Maher, Margaret R. Herubin, Mark Bluhm | 1997-05-13 |
| 5615402 | Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch | Marc A. Quattromani | 1997-03-25 |
| 5596735 | Circuit and method for addressing segment descriptor tables | Mark W. Hervin | 1997-01-21 |
| 5584009 | System and method of retiring store data from a write buffer | Marc A. Quattromani, Mark Bluhm | 1996-12-10 |
| 5572682 | Control logic for a sequential data buffer using byte read-enable lines to define and shift the access window | Douglas E. Duschatko | 1996-11-05 |
| 5524234 | Coherency for write-back cache in a system designed for write-through cache including write-back latency control | Marvin W. Martinez, Jr., Mark Bluhm, Jeffrey S. Byrne, David A. Courtright, Douglas E. Duschatko +1 more | 1996-06-04 |
| 5479616 | Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception | Mark Bluhm | 1995-12-26 |
| 5471598 | Data dependency detection and handling in a microprocessor with write buffer | Marc A. Quattromani, Nital Patwa, Mark W. Hervin | 1995-11-28 |
| 5375209 | Microprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pin | Robert Maher, Margaret R. Herubin, Mark Bluhm | 1994-12-20 |