Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12174753 | Methods and apparatus for transferring data within hierarchical cache circuitry | Joseph Michael Pusdesris, Jamshed Jalal, Dimitrios Kaseridis, Gurunath Ramagiri, Ho-Seop Kim +2 more | 2024-12-24 |
| 11841800 | Apparatus and method for handling stash requests | Jonathan Curtis Beard, Jamshed Jalal, Steven D. Krueger | 2023-12-12 |
| 11593025 | Write operation status | Gurunath Ramagiri, Jamshed Jalal, Mark David Werkheiser, Tushar P. Ringe, Ritukar Khanna | 2023-02-28 |
| 11269773 | Exclusivity in circuitry having a home node providing coherency control | Bruce James Mathewson, Phanindra Kumar Mannava, Jamshed Jalal, Andrew John Turner | 2022-03-08 |
| 11256623 | Cache content management | Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Michael Filippo, Paul Gilbert Meyer +2 more | 2022-02-22 |
| 11200177 | Cache retention data management | Alex James Waugh, Dimitrios Kaseridis, Michael Filippo, Joseph Michael Pusdesris, Jamshed Jalal | 2021-12-14 |
| 11159636 | Forwarding responses to snoop requests | Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal | 2021-10-26 |
| 11055250 | Non-forwardable transfers | Phanindra Kumar Mannava, Bruce James Mathewson, Damien Guillaume Pierre Payet, Jamshed Jalal, Alex James Waugh | 2021-07-06 |
| 10983916 | Cache storage | Huzefa Sanjeliwala, Leigang Kou, Michael Filippo, Miles Robert Dooley, Matthew A. Rafacz | 2021-04-20 |
| 10949292 | Memory interface having data signal path and tag signal path | Bruce James Mathewson, Phanindra Kumar Mannava, Michael Andrew Campbell, Alexander Alfred Hornung, Alex James Waugh +1 more | 2021-03-16 |
| 10810126 | Cache storage techniques | Joseph Michael Pusdesris, Adrian Montero, Chris Abernathy | 2020-10-20 |
| 10776043 | Storage circuitry request tracking | Adrian Montero, Miles Robert Dooley, Joseph Michael Pusdesris, Chris Abernathy | 2020-09-15 |
| 10761987 | Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operation | Jamshed Jalal, Mark David Werkheiser, Michael Filippo, Paul Gilbert Meyer | 2020-09-01 |
| 10713187 | Memory controller having data access hint message for specifying the given range of one or more memory addresses | Michael Filippo, Jamshed Jalal, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava +1 more | 2020-07-14 |
| 10613996 | Separating completion and data responses for higher read throughput and lower link utilization in a data processing network | Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Tushar P. Ringe | 2020-04-07 |
| 10579526 | Responding to snoop requests | Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal | 2020-03-03 |
| 10402349 | Memory controller having data access hint message for specifying the given range of one or more memory addresses | Michael Filippo, Jamshed Jalal, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava +1 more | 2019-09-03 |
| 10268581 | Cache hierarchy management | Michael Filippo, Vasu Kudaravalli, Adam George, Muhammad Umar Farooq, Joseph Michael Pusdesris | 2019-04-23 |
| 10223002 | Compare-and-swap transaction | Phanindra Kumar Mannava, Bruce James Mathewson, Geoffray Matthieu Lacourba | 2019-03-05 |
| 10042766 | Data processing apparatus with snoop request address alignment and snoop response time alignment | Tushar P. Ringe, Jamshed Jalal, Phanindra Kumar Mannava | 2018-08-07 |
| 9880961 | Asynchronous bridge circuitry and a method of transferring data using asynchronous bridge circuitry | Brett S. Feero | 2018-01-30 |
| 9026742 | System and method for processing potentially self-inconsistent memory transactions | Sanjay Deshpande, Michael D. Snyder | 2015-05-05 |
| 8832702 | Thread de-emphasis instruction for multithreaded processor | Sergio Schuler, Matt B. Smittle, Michael D. Snyder, Gary L. Whisenhunt | 2014-09-09 |
| 8380779 | Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand | Michael D. Snyder, Ravindraraj Ramaraju, David R. Bearden | 2013-02-19 |
| 8122437 | Method and apparatus to trace and correlate data trace and instruction trace for out-of-order processors | Zheng Xu, Suraj Bhaskaran, Jason T. Nearing, Paul B. Rawlins, Matt B. Smittle +1 more | 2012-02-21 |