Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9719861 | Temperature sensor circuit | Ravindraraj Ramaraju | 2017-08-01 |
| 9528883 | Temperature sensor circuitry with scaled voltage signal | Ravindraraj Ramaraju, Sunitha Manickavasakam, Venkataram M. Mooraka, Hector Sanchez | 2016-12-27 |
| 9367475 | System and method for cache access | Ravindraraj Ramaraju, Andrew C. Russell | 2016-06-14 |
| 9021194 | Memory management unit tag memory | Ravindraraj Ramaraju, Prashant U. Kenkare, Jogendra C. Sarker | 2015-04-28 |
| 8943292 | System and method for memory array access with fast address decoder | Ravindraraj Ramaraju, Prashant U. Kenkare | 2015-01-27 |
| 8710916 | Electronic circuit having shared leakage current reduction circuits | Ravindraraj Ramaraju, Andrew C. Russell, Shayan Zhang | 2014-04-29 |
| 8566836 | Multi-core system on chip | Ravindraraj Ramaraju, William C. Moyer | 2013-10-22 |
| 8489906 | Data processor having multiple low power modes | Ravindraraj Ramaraju, Troy L. Cooper | 2013-07-16 |
| 8380779 | Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand | Klas Magnus Bruce, Michael D. Snyder, Ravindraraj Ramaraju | 2013-02-19 |
| 8365036 | Soft error correction in a memory array and method thereof | Ravindraraj Ramaraju, Troy L. Cooper | 2013-01-29 |
| 8319548 | Integrated circuit having low power mode voltage regulator | Ravindraraj Ramaraju, Kenneth R. Burch, Charles E. Seaberg, Hector Sanchez, Bradley J. Garni | 2012-11-27 |
| 8189408 | Memory device having shifting capability and method thereof | Ravi Gupta, Ravindraraj Ramaraju | 2012-05-29 |
| 7984229 | Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access | Ravindraraj Ramaraju, Ambica Ashok, Prashant U. Kenkare | 2011-07-19 |
| 7843218 | Data latch with structural hold | Ravindraraj Ramaraju, Cody B. Croxton, Prashant U. Kenkare | 2010-11-30 |
| 7825720 | Circuit for a low power mode | Ravindraraj Ramaraju, Kenneth R. Burch, Charles E. Seaberg | 2010-11-02 |
| 7669034 | System and method for memory array access with fast address decoder | George P. Hockstra, Ravindraraj Ramaraju | 2010-02-23 |
| 7548103 | Storage device having low power mode and methods thereof | Ravindraraj Ramaraju | 2009-06-16 |
| 7542369 | Integrated circuit having a memory with low voltage read/write operation | Prashant U. Kenkare, Andrew C. Russell, James D. Burnett, Troy L. Cooper, Shayan Zhang | 2009-06-02 |
| 7523373 | Minimum memory operating voltage technique | Andrew C. Russell, Bradford Lawrence Hunter, Shayan Zhang | 2009-04-21 |
| 7292495 | Integrated circuit having a memory with low voltage read/write operation | Prashant U. Kenkare, Andrew C. Russell, James D. Burnett, Troy L. Cooper, Shayan Zhang | 2007-11-06 |
| 7215188 | Integrated circuit having a low power mode and method therefor | Ravindraraj Ramaraju, Troy L. Cooper | 2007-05-08 |
| 7187205 | Integrated circuit storage element having low power data retention and method therefor | Ravindraraj Ramaraju, Arthur R. Piejko | 2007-03-06 |
| 6493854 | Method and apparatus for placing repeaters in a network of an integrated circuit | Salim U. Chowdhury | 2002-12-10 |
| 6480998 | Iterative, noise-sensitive method of routing semiconductor nets using a delay noise threshold | Pradipto Mukherjee, Aurobindo Dasgupta, David Theodore Blaauw | 2002-11-12 |
| 6067633 | Design and methodology for manufacturing data processing systems having multiple processors | Gordon J. Robbins | 2000-05-23 |