Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9665681 | Methods and apparatus for repeater count reduction via concurrent gate sizing and repeater insertion | Guo Yu | 2017-05-30 |
| 9552454 | Concurrent timing-driven topology construction and buffering for VLSI routing | Akshay Sharma | 2017-01-24 |
| 9317641 | Gate substitution based system and method for integrated circuit power and timing optimization | Georgios Konstadinidis | 2016-04-19 |
| 8612917 | Method and system for selecting gate sizes, repeater locations, and repeater sizes of an integrated circuit | — | 2013-12-17 |
| 8176459 | System and method for selecting gates in a logic block | — | 2012-05-08 |
| 7949976 | Systematic approach for performing cell replacement in a circuit to meet timing requirements | Jingyan Zuo, Yu-Yen Mo | 2011-05-24 |
| 7454730 | Repeater insertion for concurrent setup time and hold time violations | — | 2008-11-18 |
| 6493854 | Method and apparatus for placing repeaters in a network of an integrated circuit | David R. Bearden | 2002-12-10 |