| 11226902 |
Translation load instruction with access protection |
Derek E. Williams, Benjamin Herrenschmidt, Bradly G. Frey |
2022-01-18 |
$5,274,000 |
| 10817434 |
Interruptible translation entry invalidation in a multithreaded data processing system |
Derek E. Williams, Benjamin Herrenschmidt, Bradly G. Frey |
2020-10-27 |
$6,165,000 |
| 10613792 |
Efficient enforcement of barriers with respect to memory move sequences |
Bradly G. Frey, Guy L. Guthrie, William J. Starke, Derek E. Williams |
2020-04-07 |
$1,846,000 |
| 10387686 |
Hardware based isolation for secure execution of virtual machines |
Richard H. Boivie, Bradly G. Frey, William E. Hall, Benjamin Herrenschmidt, Guerney D. H. Hunt +3 more |
2019-08-20 |
$1,949,000 |
| 10152322 |
Memory move instruction sequence including a stream of copy-type and paste-type instructions |
Bradly G. Frey, Sanjeev Ghai, Guy L. Guthrie, William J. Starke, Derek E. Williams |
2018-12-11 |
$6,670,000 |
| 10067713 |
Efficient enforcement of barriers with respect to memory move sequences |
Bradly G. Frey, Guy L. Guthrie, William J. Starke, Derek E. Williams |
2018-09-04 |
$2,923,000 |
| 9785557 |
Translation entry invalidation in a multithreaded data processing system |
Bradly G. Frey, Guy L. Guthrie, Derek E. Williams |
2017-10-10 |
$2,342,000 |
| 9772945 |
Translation entry invalidation in a multithreaded data processing system |
Bradly G. Frey, Guy L. Guthrie, Derek E. Williams |
2017-09-26 |
$3,108,000 |
| 9626187 |
Transactional memory system supporting unbroken suspended execution |
Harold W. Cain, III, Bradly G. Frey, Benjamin Herrenschmidt, Hung Q. Le, Maged M. Michael +4 more |
2017-04-18 |
$1,813,000 |
| 9626256 |
Determining failure context in hardware transactional memories |
Harold W. Cain, III, Bradly G. Frey, Hung Q. Le |
2017-04-18 |
$1,813,000 |
| 9619345 |
Apparatus for determining failure context in hardware transactional memories |
Harold W. Cain, III, Bradly G. Frey, Hung Q. Le |
2017-04-11 |
$2,654,000 |
| 9430166 |
Interaction of transactional storage accesses with other atomic semantics |
Bradly G. Frey, Guy L. Guthrie, Derek E. Williams |
2016-08-30 |
$3,867,000 |
| 9396115 |
Rewind only transactions in a data processing system supporting transactional storage accesses |
Robert J. Blainey, Bradly G. Frey, Guy L. Guthrie, Derek E. Williams |
2016-07-19 |
$4,161,000 |
| 9367263 |
Transaction check instruction for memory transactions |
Bradly G. Frey, Guy L. Guthrie, Derek E. Williams |
2016-06-14 |
$6,457,000 |
| 9367264 |
Transaction check instruction for memory transactions |
Bradly G. Frey, Guy L. Guthrie, Derek E. Williams |
2016-06-14 |
$6,457,000 |
| 9342454 |
Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accesses |
Bradly G. Frey, Guy L. Guthrie, Derek E. Williams |
2016-05-17 |
$3,602,000 |
| 9268599 |
Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories |
Robert J. Blainey, Harold W. Cain, III, Susan E. Eisen, Bradley G. Frey, Charles B. Hall +1 more |
2016-02-23 |
$5,149,000 |
| 9268598 |
Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories |
Robert J. Blainey, Harold W. Cain, III, Susan E. Eisen, Bradly G. Frey, Charles B. Hall +1 more |
2016-02-23 |
$5,149,000 |
| 9244846 |
Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses |
Bradly G. Frey, Derek E. Williams |
2016-01-26 |
$2,109,000 |
| 9081607 |
Conditional transaction abort and precise abort handling |
Robert J. Blainey, Harold W. Cain, III, Bradly G. Frey, Hung Q. Le |
2015-07-14 |
$7,900,000 |
| 9047079 |
Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition |
Becky Bruce, Giles R. Frazier, Bradly G. Frey, Kumar K. Gala, Michael D. Snyder +2 more |
2015-06-02 |
$4,815,000 |
| 8745307 |
Multiple page size segment encoding |
Sundeep Chadha, Naresh Nayar, Randal C. Swanberg |
2014-06-03 |
$4,638,000 |
| 8615644 |
Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition |
Becky Bruce, Giles R. Frazier, Bradly G. Frey, Kumar K. Gala, Michael D. Snyder +2 more |
2013-12-24 |
$7,453,000 |
| 8544022 |
Transactional memory preemption mechanism |
Richard Louis Arndt, Harold W. Cain, III, Bradly G. Frey |
2013-09-24 |
$6,780,000 |
| 8424015 |
Transactional memory preemption mechanism |
Richard Louis Arndt, Harold W. Cain, III, Bradly G. Frey |
2013-04-16 |
$3,567,000 |
