Issued Patents All Time
Showing 26–38 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8176254 | Specifying an access hint for prefetching limited use data in a cache hierarchy | Bradly G. Frey, Guy L. Guthrie, Balaram Sinharoy, Peter K. Szwed | 2012-05-08 |
| 8140759 | Specifying an access hint for prefetching partial cache block data in a cache hierarchy | Bradly G. Frey, Guy L. Guthrie, Ramakrishnan Rajamony, Balaram Sinharoy, William J. Starke +1 more | 2012-03-20 |
| 8010763 | Hypervisor-enforced isolation of entities within a single logical partition's virtual address space | William J. Armstrong, Orran Krieger, Michal Ostrowski, Randal C. Swanberg | 2011-08-30 |
| 7949859 | Mechanism for avoiding check stops in speculative accesses while operating in real mode | Ronald Nick Kalla, Balaram Sinharoy, Edward John Silha, Shih-Hsiung S. Tung | 2011-05-24 |
| 7904661 | Data stream prefetching in a microprocessor | Eric Jason Fluhr, Bradly G. Frey, John B. Griswell, Jr., Hung Q. Le, Francis Patrick O'Connell +2 more | 2011-03-08 |
| 7822942 | Selectively invalidating entries in an address translation cache | Michael J. Corrigan, Paul LuVerne Godtland, Joaquin Hinojosa, Naresh Nayar, Edward John Silha | 2010-10-26 |
| 7802252 | Method and apparatus for selecting the architecture level to which a processor appears to conform | William J. Armstrong, Richard Louis Arndt, Michael J. Corrigan, Giles R. Frazier, Timothy R. Marchini +2 more | 2010-09-21 |
| 7389400 | Apparatus and method for selectively invalidating entries in an address translation cache | Michael J. Corrigan, Paul LuVerne Godtland, Joaquin Hinojosa, Naresh Nayar, Edward John Silha | 2008-06-17 |
| 7370177 | Mechanism for avoiding check stops in speculative accesses while operating in real mode | Ronald Nick Kalla, Balaram Sinharoy, Edward John Silha, Shih-Hsiung S. Tung | 2008-05-06 |
| 7350029 | Data stream prefetching in a microprocessor | Eric Jason Fluhr, Bradly G. Frey, John B. Griswell, Jr., Hung Q. Le, Francis Patrick O'Connell +2 more | 2008-03-25 |
| 7143267 | Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor | Eric Jason Fluhr, Balaram Sinharoy | 2006-11-28 |
| 6823445 | Limiting concurrent modification and execution of instructions to a particular type to avoid unexpected results | Edward John Silha | 2004-11-23 |
| 6202130 | Data processing system for processing vector data and method therefor | Hunter Ledbetter Scales, III, Keith E. Diefendorff, Brett Olsson, Pradeep Kumar Dubey, Ronald Ray Hochsprung +4 more | 2001-03-13 |