Issued Patents All Time
Showing 1–25 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7666752 | Deposition method for a transition-metal-containing dielectric | Lars Oberbeck, Uwe Schroeder, Tim Boescke, Johannes Heitmann, Annette Saenger +2 more | 2010-02-23 |
| 7531418 | Method of producing a conductive layer including two metal nitrides | Bernd Hintze, Jonas Sundqvist | 2009-05-12 |
| 7413951 | Stacked capacitor and method for producing stacked capacitors for dynamic memory cells | Peter Moll, Stefan Jakschik, Odo Wunnicke | 2008-08-19 |
| 7402860 | Method for fabricating a capacitor | Christian Kapteyn, Thomas Hecht | 2008-07-22 |
| 7312114 | Manufacturing method for a trench capacitor having an isolation collar electrically connected with a substrate on a single side via a buried contact for use in a semiconductor memory cell | Guenther Aichmayr | 2007-12-25 |
| 7273790 | Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell | Martin Popp, Harald Seidl, Annette Sanger | 2007-09-25 |
| 7189614 | Method for fabricating a trench structure which is electrically connected to a substrate on one side via a buried contact | Albrecht Kieslich, Kevin Pears | 2007-03-13 |
| 7157329 | Trench capacitor with buried strap | Helmut Tews, Jochen Beintner | 2007-01-02 |
| 7157371 | Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices | Thomas Hecht, Uwe Schroeder, Harald Seidl, Martin Gutsche, Stefan Jakschik +1 more | 2007-01-02 |
| 7157382 | Method for expanding a trench in a semiconductor structure | — | 2007-01-02 |
| 7157328 | Selective etching to increase trench surface area | Helmut Tews, Kenneth T. Settlemyer, Jr. | 2007-01-02 |
| 6974743 | Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates | Ramac Divakaruni, Jack A. Mandelman | 2005-12-13 |
| 6953722 | Method for patterning ceramic layers | Harald Seidl, Martin Gutsche, Thomas Hecht, Stefan Jakschik, Uwe Schroder +1 more | 2005-10-11 |
| 6927172 | Process to suppress lithography at a wafer edge | Wolfgang Bergner, Linda A. Chen, Franz Zach | 2005-08-09 |
| 6919255 | Semiconductor trench structure | Albert Birner, Matthias Goldbach, Thomas Hecht, Lars Heineck, Jorn Lutzen +2 more | 2005-07-19 |
| 6916721 | Method for fabricating a trench capacitor with an insulation collar | Lars Heineck, Jorn Lutzen, Hans-Peter Moll, Martin Popp, Till Schlosser +1 more | 2005-07-12 |
| 6853025 | Trench capacitor with buried strap | Helmut Tews, Jochen Beintner | 2005-02-08 |
| 6740555 | Semiconductor structures and manufacturing methods | Helmut Tews, Alexander Michaelis, Uwe Schroeder, Raj Jammy, Ulrike Gruening | 2004-05-25 |
| 6740595 | Etch process for recessing polysilicon in trench structures | Helmut Tews, Alexander Michaelis, Uwe Schroeder, Martin Popp, Kristin Schupke +1 more | 2004-05-25 |
| 6677197 | High aspect ratio PBL SiN barrier formation | Helmut Tews | 2004-01-13 |
| 6670235 | Process flow for two-step collar in DRAM preparation | Helmut Tews, Oliver Genz | 2003-12-30 |
| 6613642 | Method for surface roughness enhancement in semiconductor capacitor manufacturing | Stephen Rahn, Irene McStay, Helmut Tews, Uwe Schroeder, Rajarao Jammy | 2003-09-02 |
| 6605860 | Semiconductor structures and manufacturing methods | Helmut Tews, Alexander Michaelis, Uwe Schroeder, Raj Jammy, Ulrike Gruening | 2003-08-12 |
| 6605838 | Process flow for thick isolation collar with reduced length | Jack A. Mandelman, Rama Divakaruni, Gerd Fehlauer, Uwe Schroeder, Helmut Tews | 2003-08-12 |
| 6599798 | Method of preparing buried LOCOS collar in trench DRAMS | Helmut Tews, Uwe Schroeder, Rolf Weis | 2003-07-29 |