Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6573137 | Single sided buried strap | Ramachandra Divakaruni, Jack A. Mandelman, Wolfgang Bergner, Gary B. Bronner, Ulrike Gruening +5 more | 2003-06-03 |
| 6566273 | Etch selectivity inversion for etching along crystallographic directions in silicon | — | 2003-05-20 |
| 6559002 | Rough oxide hard mask for DT surface area enhancement for DT DRAM | Helmut Tews, Stephen Rahn, Irene McStay, Uwe Schroeder | 2003-05-06 |
| 6555430 | Process flow for capacitance enhancement in a DRAM trench | Michael P. Chudzik, Johnathan E. Faltermeier, Rajarao Jammy, Irene McStay, Kenneth T. Settlemyer, Jr. +1 more | 2003-04-29 |
| 6548344 | Spacer formation process using oxide shield | Jochen Beintner, Thomas W. Dyer | 2003-04-15 |
| 6518616 | Vertical gate top engineering for improved GC and CB process windows | Thomas W. Dyer, Venkatachaiam C. Jaiprakash, Carl Radens | 2003-02-11 |
| 6498061 | Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation | Rama Divakaruni, Helmut Tews, Irene McStay, Kil-Ho Lee, Uwe Schroeder | 2002-12-24 |
| 6486024 | Integrated circuit trench device with a dielectric collar stack, and method of forming thereof | Helmut Tews, Alexander Michaelis, Uwe Schroeder, Ulrike Gruening | 2002-11-26 |
| 6458647 | Process flow for sacrificial collar with poly mask | Helmut Tews, Irene McStay | 2002-10-01 |
| 6440872 | Method for hybrid DRAM cell utilizing confined strap isolation | Jack A. Mandelman, Ramachandra Divakaruni, Carl Radens | 2002-08-27 |
| 6437401 | Structure and method for improved isolation in trench storage cells | Jack A. Mandelman, Andreas Knorr, Stephen Rahn, Helmut Tews, Michael Wise | 2002-08-20 |
| 6426253 | Method of forming a vertically oriented device in an integrated circuit | Helmut Tews, Alexander Michaelis, Brian Lee, Uwe Schroeder | 2002-07-30 |
| 6406970 | Buried strap formation without TTO deposition | Helmut Tews | 2002-06-18 |
| 6352893 | Low temperature self-aligned collar formation | Alexander Michaelis, Jochen Beintner, Oliver Genz | 2002-03-05 |
| 6335247 | Integrated circuit vertical trench device and method of forming thereof | Helmut Tews, Alexander Michaelis, Uwe Schroeder, Brian Lee | 2002-01-01 |
| 6309983 | Low temperature sacrificial oxide formation | Alexander Michaeli | 2001-10-30 |
| 6295998 | Temperature controlled gassification of deionized water for megasonic cleaning of semiconductor wafers | David L. Rath | 2001-10-02 |
| 6284666 | Method of reducing RIE lag for deep trench silicon etching | Munir D. Naeem, Gangadhara S. Mathad, Byeong Y. Kim, Brian Lee, Heon Lee +3 more | 2001-09-04 |
| 6261972 | Dual gate oxide process for uniform oxide thickness | Helmut Tews, Mary E. Weybright, Oleg Gluschenkov, Suri Hegde | 2001-07-17 |
| 6167891 | Temperature controlled degassification of deionized water for megasonic cleaning of semiconductor wafers | David L. Rath | 2001-01-02 |
| 6096664 | Method of manufacturing semiconductor structures including a pair of MOSFETs | Thomas Rupp, Jeffrey P. Gambino, Mary E. Weybright | 2000-08-01 |
| 6066527 | Buried strap poly etch back (BSPE) process | Alexander Michaelis | 2000-05-23 |