GM

Gangadhara S. Mathad

IBM: 22 patents #4,909 of 70,183Top 7%
Infineon Technologies Ag: 6 patents #1,696 of 7,486Top 25%
Overall (All Time): #165,652 of 4,157,543Top 4%
25
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7144769 Method to achieve increased trench depth, independent of CD as defined by lithography Kevin K. Chan, Subhash B. Kulkarni, Rajiv Ranade 2006-12-05
6842235 Optical measurement of planarized features Syed Zaidi 2005-01-11
6821864 Method to achieve increased trench depth, independent of CD as defined by lithography Kevin K. Chan, Subhash B. Kulkarni, Rajiv Ranade 2004-11-23
6821900 Method for dry etching deep trenches in a substrate Satish D. Athavale, Rajiv Ranade, Munir D. Naeem 2004-11-23
6809005 Method to fill deep trench structures with void-free polysilicon or silicon Rajiv Ranade, Kevin K. Chan, Subhash B. Kulkarni 2004-10-26
6743727 Method of etching high aspect ratio openings Siddhartha Panda, Rajiv Ranade 2004-06-01
6709917 Method to increase the etch rate and depth in high aspect ratio structure Siddhartha Panda, Rajiv Ranade 2004-03-23
6687014 Method for monitoring the rate of etching of a semiconductor Shoaib Zaidi 2004-02-03
6544838 Method of deep trench formation with improved profile control and surface area Rajiv Ranade, Munir D. Naeem 2003-04-08
6489249 Elimination/reduction of black silicon in DT etch Rajiv Ranade 2002-12-03
6284666 Method of reducing RIE lag for deep trench silicon etching Munir D. Naeem, Byeong Y. Kim, Stephan Kudelka, Brian Lee, Heon Lee +3 more 2001-09-04
6224690 Flip-Chip interconnections using lead-free solders Panayotis Andricacos, Madhav Datta, Hariklia Deligianni, Wilma Jean Horkans, Sung Kwon Kang +4 more 2001-05-01
5759437 Etching of Ti-W for C4 rework Madhav Datta, Thomas S. Kanarsky, Ravindra V. Shenoy 1998-06-02
5391510 Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps Louis L. Hsu, Rajiv V. Joshi 1995-02-21
5258264 Process of forming a dual overhang collimated lift-off stencil with subsequent metal deposition David Stanasolovich, Giorgio G. Via 1993-11-02
5024896 Collimated metal deposition David Stanasolovich, Giorgio G. Via 1991-06-18
4741799 Anisotropic silicon etching in fluorinated plasma Lee Chen 1988-05-03
4671849 Method for control of etch profile Lee Chen 1987-06-09
4617730 Method of fabricating a chip interposer Pieter Geldermans 1986-10-21
4602981 Monitoring technique for plasma etching Lee Chen 1986-07-29
4534816 Single wafer plasma etch reactor Lee Chen, Charles J. Hendricks, Stanley J. Poloncic 1985-08-13
4511430 Control of etch rate ratio of SiO.sub.2 /photoresist for quartz planarization etch back process Lee Chen 1985-04-16
4490210 Laser induced dry chemical etching of metals Lee Chen, Tung J. Chuang 1984-12-25
4490211 Laser induced chemical etching of metals with excimer lasers Lee Chen, John R. Lankard, Sr. 1984-12-25
4478677 Laser induced dry etching of vias in glass with non-contact masking Lee Chen, Tung J. Chuang 1984-10-23