Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12336288 | Array of vertical transistors and method used in forming an array of vertical transistors | Yi Fang Lee, Jaydip Guha, Kamal M. Karda, Si-Woo Lee, Terrence B. McDaniel +3 more | 2025-06-17 |
| 12237259 | Electronic devices comprising multilevel bitlines, and related methods and systems | Yoshiaki Fukuzumi, Harsh Narendrakumar Jain, Naveen Kaushik, Adam L. Olson, Richard J. Hill | 2025-02-25 |
| 12166094 | Microelectronic devices with active source/drain contacts in trench in symmetrical dual-block structure, and related systems and methods | Lifang Xu, Richard J. Hill, Indra V. Chary | 2024-12-10 |
| 11514953 | Integrated assemblies, and methods of forming integrated assemblies | Yoshiaki Fukuzumi, Paolo Tessariol, David H. Wells, Richard J. Hill, Lifang Xu +2 more | 2022-11-29 |
| 11488981 | Array of vertical transistors and method used in forming an array of vertical transistors | Yi Fang Lee, Jaydip Guha, Kamal M. Karda, Si-Woo Lee, Terrence B. McDaniel +3 more | 2022-11-01 |
| 10937690 | Selective dielectric deposition | Anish A. Khandekar, Silvia Borsari, Zhiqiang Xie | 2021-03-02 |
| 10566332 | Semiconductor devices | Kuo-Chen Wang, Shih-Fan Kuan, Sanh D. Tang | 2020-02-18 |
| 10163909 | Methods for fabricating a semiconductor memory device | Kuo-Chen Wang, Shih-Fan Kuan, Sanh D. Tang | 2018-12-25 |
| 9881924 | Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and method for fabricating the same | Kuo-Chen Wang, Shih-Fan Kuan, Sanh D. Tang | 2018-01-30 |
| 9691773 | Silicon buried digit line access device and method of forming the same | Shyam Surthi | 2017-06-27 |
| 9391092 | Circuit structures, memory circuitry, and methods | John K. Zahurak, Sanh D. Tang, Martin C. Roberts, Wolfgang Mueller, Haitao Liu | 2016-07-12 |
| 9385132 | Arrays of recessed access devices, methods of forming recessed access gate constructions, and methods of forming isolation gate constructions in the fabrication of recessed access devices | Troy Sorensen | 2016-07-05 |
| 9337201 | Memory cells, arrays of memory cells, and methods of forming memory cells | Jaydip Guha | 2016-05-10 |
| 9318493 | Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions | Shyam Surthi, Jaydip Guha | 2016-04-19 |
| 9269795 | Circuit structures, memory circuitry, and methods | John K. Zahurak, Sanh D. Tang, Martin C. Roberts, Wolfgang Mueller, Haitao Liu | 2016-02-23 |
| 9263317 | Method of forming buried word line structure | Inho Park | 2016-02-16 |
| 9070584 | Buried digitline (BDL) access device and memory array | Shyam Surthi | 2015-06-30 |
| 9036391 | Arrays of vertically-oriented transistors, memory arrays including vertically-oriented transistors, and memory cells | Jonathan Doebler | 2015-05-19 |
| 9012330 | Method for semiconductor cross pitch doubled patterning process | Vinay Nair | 2015-04-21 |
| 8871589 | Methods of forming semiconductor constructions | Shyam Surthi, Jaydip Guha | 2014-10-28 |
| 8772848 | Circuit structures, memory circuitry, and methods | John K. Zahurak, Sanh D. Tang, Martin C. Roberts, Wolfgang Mueller, Haitao Liu | 2014-07-08 |
| 8735267 | Buried word line structure and method of forming the same | Inho Park | 2014-05-27 |
| 8569831 | Integrated circuit arrays and semiconductor constructions | Shyam Surthi, Jaydip Guha | 2013-10-29 |
| 8502294 | Semiconductor process and semiconductor structure for memory array with buried digit lines (BDL) | Shyam Surthi | 2013-08-06 |
| 8450207 | Method of fabricating a cell contact and a digit line for a semiconductor device | Shyam Surthi | 2013-05-28 |