Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11462544 | Array of recessed access gate lines | Sanh D. Tang, Kamal M. Karda, Sourabh Dhir, Robert Kerr, Sangmin Hwang +1 more | 2022-10-04 |
| 10163908 | Array of conductive lines individually extending transversally across and elevationally over a mid-portion of individual active area regions | Sanh D. Tang, Kamal M. Karda, Sourabh Dhir, Robert Kerr, Sangmin Hwang +1 more | 2018-12-25 |
| 9812455 | Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias | Sanh D. Tang, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak | 2017-11-07 |
| 9773888 | Vertical access devices, semiconductor device structures, and related methods | Srinivas Pulugurtha, Haitao Liu, Sanh D. Tang, Sourabh Dhir | 2017-09-26 |
| 9589962 | Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias | Sanh D. Tang, Brent Gilgen, Dylan R. Macmaster, Jim A. Jozwiak | 2017-03-07 |
| 9577092 | Apparatuses having a vertical memory cell | Kamal M. Karda, Rajesh N. Gupta, Srinivas Pulugurtha, Chandra Mouli | 2017-02-21 |
| 9564442 | Methods of forming contacts for a semiconductor device structure, and related methods of forming a semiconductor device structure | Sanh D. Tang, Sourabh Dhir, Dylan R. Macmaster | 2017-02-07 |
| 9478550 | Arrays of vertically-oriented transistors, and memory arrays including vertically-oriented transistors | Kamal M. Karda, Shyam Surthi, Sanh D. Tang | 2016-10-25 |
| 9472542 | DRAM arrays, semiconductor constructions and DRAM array layouts | Sanh D. Tang | 2016-10-18 |
| 9391092 | Circuit structures, memory circuitry, and methods | John K. Zahurak, Sanh D. Tang, Lars Heineck, Martin C. Roberts, Haitao Liu | 2016-07-12 |
| 9373715 | Semiconductor devices including vertical memory cells and methods of forming same | Sanh D. Tang, Sourabh Dhir, Srinivas Pulugurtha | 2016-06-21 |
| 9269795 | Circuit structures, memory circuitry, and methods | John K. Zahurak, Sanh D. Tang, Lars Heineck, Martin C. Roberts, Haitao Liu | 2016-02-23 |
| 9263455 | Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines | Sanh D. Tang, Kamal M. Karda, Sourabh Dhir, Robert Kerr, Sangmin Hwang +1 more | 2016-02-16 |
| 8878271 | Vertical access device and apparatuses having a body connection line, and related method of operating the same | Kamal M. Karda, Rajesh N. Gupta, Srinivas Pulugurtha, Chandra Mouli | 2014-11-04 |
| 8772848 | Circuit structures, memory circuitry, and methods | John K. Zahurak, Sanh D. Tang, Lars Heineck, Martin C. Roberts, Haitao Liu | 2014-07-08 |
| 8769120 | Method and system to monitor parameters of a data flow path in a communication system | Oumar Traore, Michael Uckermann | 2014-07-01 |
| 7727837 | Method of producing an integrated circuit having a capacitor with a supporting layer | Ulrike Gruening-von Schwerin, Rolf Weis, Wolfgang Henke, Odo Wunnicke, Till Schloesser +1 more | 2010-06-01 |
| 7301192 | Dram cell pair and dram memory cell array | Johann Harter, Wolfgang Bergner, Ulrike Grüning Von Schwerin, Till Schloesser, Rolf Weis | 2007-11-27 |
| 7141845 | DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same | Dirk Manger, Till Schloesser, Rolf Weis, Bernd Goebel | 2006-11-28 |
| 6408512 | Method of correcting deformed turbine blades | Andreas Boegli, Markus Schmid | 2002-06-25 |
| 5458742 | Isolation of fullerenes | Uwe Wirth, Joachim Semel | 1995-10-17 |
| 5025295 | Three-dimensional one-dimensional cell arrangement for dynamic semiconductor memories and method for the manufacture of a bit line contact | Karl-Heinz Kuesters, Gerd Enders | 1991-06-18 |
| 4966859 | Voltage-stable sub-.mu.m MOS transistor for VLSI circuits | Lothar Risch, Reinhard Tielert, Christoph Werner | 1990-10-30 |
| 4763301 | Integrated dynamic semiconductor memory with complementary circuitry and word line voltage control | Alfred Schuetz, Ewald Soutschek | 1988-08-09 |
| 4760033 | Method for the manufacture of complementary MOS field effect transistors in VLSI technology | — | 1988-07-26 |