Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8546920 | Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) | Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Jeffrey W. Sleight | 2013-10-01 |
| 8288826 | Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) | Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Jeffrey W. Sleight | 2012-10-16 |
| 8101150 | Control of carbon nanotube diameter using CVD or PECVD growth | Alfred Grill, Deborah A. Neumayer | 2012-01-24 |
| 8053373 | Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX) | Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Jeffrey W. Sleight | 2011-11-08 |
| 8021956 | Ultrathin SOI CMOS devices employing differential STI liners | Zhibin Ren, Ghavam G. Shahidi, Jeffrey W. Sleight, Xinhui Wang | 2011-09-20 |
| 8012820 | Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension | Amlan Majumdar, Gen Pei, Zhibin Ren, Jeffrey W. Sleight | 2011-09-06 |
| 7776624 | Method for improving semiconductor surfaces | Ashima B. Chakravarti, Judson R. Holt, Jeremy J. Kempisty, Suk Hoon Ku, Woo-Hyeong Lee +4 more | 2010-08-17 |
| 7713837 | Low temperature fusion bonding with high surface energy using a wet chemical treatment | Kevin K. Chan, Kathryn Guarini, Erin C. Jones, Antonio F. Saavedra, Jr., Leathen Shi | 2010-05-11 |
| 7687863 | Selective incorporation of charge for transistor channels | John Michael Hergenrother, Zhibin Ren, Jeffrey W. Sleight | 2010-03-30 |
| 7659583 | Ultrathin SOI CMOS devices employing differential STI liners | Zhibin Ren, Ghavam G. Shahidi, Jeffrey W. Sleight, Xinhui Wang | 2010-02-09 |
| 7628974 | Control of carbon nanotube diameter using CVD or PECVD growth | Alfred Grill, Deborah A. Neumayer | 2009-12-08 |
| 7566631 | Low temperature fusion bonding with high surface energy using a wet chemical treatment | Kevin K. Chan, Kathryn Guarini, Erin C. Jones, Antonio F. Saavedra, Jr., Leathen Shi | 2009-07-28 |
| 7396776 | Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) | Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Jeffrey W. Sleight | 2008-07-08 |
| 7374998 | Selective incorporation of charge for transistor channels | John Michael Hergenrother, Zhibin Ren, Jeffrey W. Sleight | 2008-05-20 |
| 6972440 | Enhanced T-gate structure for modulation doped field effect transistors | Katherine L. Saenger, Vishnubhai V. Patel, Alfred Grill, Steven J. Koester | 2005-12-06 |
| 6911375 | Method of fabricating silicon devices on sapphire with wafer bonding at low temperature | Kathryn Guarini, Louis L. Hsu, Leathen Shi, Li-Kong Wang | 2005-06-28 |
| 6740535 | Enhanced T-gate structure for modulation doped field effect transistors | Katherine L. Saenger, Vishnubhai V. Patel, Alfred Grill, Steven J. Koester | 2004-05-25 |