Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
DS

Dinkar Singh — 17 Patents

IBM: 17 patents #6,529 of 70,183Top 10%
AMD: 1 patents #7,027 of 9,280Top 80%
White Plains, NY: #120 of 917 inventorsTop 15%
New York: #8,526 of 115,490 inventorsTop 8%
Overall (All Time): #263,971 of 4,157,543Top 7%
17 Patents All Time
Dinkar Singh has been granted 17 US patents while listed as an inventor at IBM. The first was granted in 2004 and the most recent in October 2013. Dinkar Singh ranks #263,971 of 4,157,543 US inventors in our database (top 6.3%). Patent records list Dinkar Singh in White Plains, NY, US.

Patents per Year

Patents granted per year, 2004 to 2013Bar chart with a peak of 4 patents in 2010.peak 42004: 1 patents20042005: 2 patents20052008: 2 patents20082009: 2 patents20092010: 4 patents20102011: 3 patents20112012: 2 patents20122013: 1 patents2013

Issued Patents All Time

Showing 1–17 of 17 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8546920 Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Jeffrey W. Sleight 2013-10-01 $5,042,000
8288826 Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Jeffrey W. Sleight 2012-10-16 $3,795,000
8101150 Control of carbon nanotube diameter using CVD or PECVD growth Alfred Grill, Deborah A. Neumayer 2012-01-24 $7,514,000
8053373 Semiconductor-on-insulator(SOI) structures including gradient nitrided buried oxide (BOX) Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Jeffrey W. Sleight 2011-11-08 $3,097,000
8021956 Ultrathin SOI CMOS devices employing differential STI liners Zhibin Ren, Ghavam G. Shahidi, Jeffrey W. Sleight, Xinhui Wang 2011-09-20 $5,575,000
8012820 Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension Amlan Majumdar, Gen Pei, Zhibin Ren, Jeffrey W. Sleight 2011-09-06
7776624 Method for improving semiconductor surfaces Ashima B. Chakravarti, Judson R. Holt, Jeremy J. Kempisty, Suk Hoon Ku, Woo-Hyeong Lee +4 more 2010-08-17 $4,695,000
7713837 Low temperature fusion bonding with high surface energy using a wet chemical treatment Kevin K. Chan, Kathryn Guarini, Erin C. Jones, Antonio F. Saavedra, Jr., Leathen Shi 2010-05-11 $5,650,000
7687863 Selective incorporation of charge for transistor channels John Michael Hergenrother, Zhibin Ren, Jeffrey W. Sleight 2010-03-30 $5,470,000
7659583 Ultrathin SOI CMOS devices employing differential STI liners Zhibin Ren, Ghavam G. Shahidi, Jeffrey W. Sleight, Xinhui Wang 2010-02-09 $5,437,000
7628974 Control of carbon nanotube diameter using CVD or PECVD growth Alfred Grill, Deborah A. Neumayer 2009-12-08 $16,023,000
7566631 Low temperature fusion bonding with high surface energy using a wet chemical treatment Kevin K. Chan, Kathryn Guarini, Erin C. Jones, Antonio F. Saavedra, Jr., Leathen Shi 2009-07-28 $11,761,000
7396776 Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Jeffrey W. Sleight 2008-07-08 $9,414,000
7374998 Selective incorporation of charge for transistor channels John Michael Hergenrother, Zhibin Ren, Jeffrey W. Sleight 2008-05-20 $8,483,000
6972440 Enhanced T-gate structure for modulation doped field effect transistors Katherine L. Saenger, Vishnubhai V. Patel, Alfred Grill, Steven J. Koester 2005-12-06 $7,444,000
6911375 Method of fabricating silicon devices on sapphire with wafer bonding at low temperature Kathryn Guarini, Louis L. Hsu, Leathen Shi, Li-Kong Wang 2005-06-28 $7,000,000
6740535 Enhanced T-gate structure for modulation doped field effect transistors Katherine L. Saenger, Vishnubhai V. Patel, Alfred Grill, Steven J. Koester 2004-05-25 $11,301,000