| 8120138 |
High-Z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
David M. Fried, Sharee McNab, Michael J. Rooks, Anna W. Topol |
2012-02-21 |
| 7943486 |
Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain |
Victor Chan, Massimo V. Fischetti, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek +3 more |
2011-05-17 |
| 7859061 |
Halo-first ultra-thin SOI FET for superior short channel control |
Omer H. Dokumaci, Shreesh Narasimha, Jeffrey W. Sleight |
2010-12-28 |
| 7696057 |
Method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
David M. Fried, Sharee McNab, Michael J. Rooks, Anna W. Topol |
2010-04-13 |
| 7687863 |
Selective incorporation of charge for transistor channels |
Zhibin Ren, Dinkar Singh, Jeffrey W. Sleight |
2010-03-30 |
| 7595247 |
Halo-first ultra-thin SOI FET for superior short channel control |
Omer H. Dokumaci, Shreesh Narasimha, Jeffrey W. Sleight |
2009-09-29 |
| 7550361 |
Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels |
David M. Fried, Sharee McNab, Michael J. Rooks, Anna W. Topol |
2009-06-23 |
| 7462525 |
Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain |
Victor Chan, Massimo V. Fischetti, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek +3 more |
2008-12-09 |
| 7374998 |
Selective incorporation of charge for transistor channels |
Zhibin Ren, Dinkar Singh, Jeffrey W. Sleight |
2008-05-20 |
| 7314790 |
Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain |
Victor Chan, Massimo V. Fischetti, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek +3 more |
2008-01-01 |
| 7161169 |
Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain |
Victor Chan, Massimo V. Fischetti, Meikei Leong, Rajesh Rengarajan, Alexander Reznicek +3 more |
2007-01-09 |
| 6903411 |
Architecture for circuit connection of a vertical transistor |
Yih-Feng Chyan, Donald Monroe |
2005-06-07 |
| 6828628 |
Diffused MOS devices with strained silicon portions and methods for forming same |
Muhammed Ayman Shibib, Shuming Xu, Zhijian Xie |
2004-12-07 |
| 6821851 |
Method of making ultra thin body vertical replacement gate MOSFET |
Pranav Kalavade |
2004-11-23 |
| 6653181 |
CMOS integrated circuit having vertical transistors and a process for fabricating same |
Donald Monroe |
2003-11-25 |
| 6635924 |
Ultra thin body vertical replacement gate MOSFET |
Pranav Kalavade |
2003-10-21 |
| 6518622 |
Vertical replacement gate (VRG) MOSFET with a conductive layer adjacent a source/drain region and method of manufacture therefor |
Hongzong Chew, Yih-Feng Chyan, Yi Ma, Donald Monroe |
2003-02-11 |
| 6197641 |
Process for fabricating vertical transistors |
Donald Monroe, Gary Robert Weber |
2001-03-06 |
| 6027975 |
Process for fabricating vertical transistors |
Donald Monroe |
2000-02-22 |