Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9373548 | CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer | Scott Luning, Johannes M. van Meer | 2016-06-21 |
| 8400854 | Identifying at-risk data in non-volatile storage | Lanlan Gu, Nima Mokhlesi, Idan Alrod, Eran Sharon, Itshak Afriat | 2013-03-19 |
| 8012820 | Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extension | Amlan Majumdar, Zhibin Ren, Dinkar Singh, Jeffrey W. Sleight | 2011-09-06 |
| 7943999 | Stress enhanced MOS circuits | — | 2011-05-17 |
| 7816767 | Negative differential resistance diode and SRAM utilizing such device | Zoran Krivokapic | 2010-10-19 |
| 7508050 | Negative differential resistance diode and SRAM utilizing such device | Zoran Krivokapic | 2009-03-24 |
| 7442601 | Stress enhanced CMOS circuits and methods for their fabrication | Scott Luning, Johannes M. van Meer | 2008-10-28 |
| 7439120 | Method for fabricating stress enhanced MOS circuits | — | 2008-10-21 |
| 7416931 | Methods for fabricating a stress enhanced MOS circuit | — | 2008-08-26 |