Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8452897 | Method for using a multi-master multi-slave bus for power management | Kenneth W. Fernald, James W. Templeton | 2013-05-28 |
| 8239597 | Device-to-device communication bus for distributed power management | — | 2012-08-07 |
| 7908402 | Integrated multi-function point-of-load regulator circuit | Kenneth W. Fernald, James W. Templeton | 2011-03-15 |
| 7793005 | Power management system using a multi-master multi-slave bus and multi-function point-of-load regulators | Kenneth W. Fernald, James W. Templeton | 2010-09-07 |
| 7685320 | Autonomous sequencing and fault spreading | — | 2010-03-23 |
| 7653757 | Method for using a multi-master multi-slave bus for power management | Kenneth W. Fernald, James W. Templeton | 2010-01-26 |
| 7522620 | Method and apparatus for scheduling packets | Sanjeev Kumar Jain, David Romano | 2009-04-21 |
| 7426215 | Method and apparatus for scheduling packets | David Romano, Sanjeev Kumar Jain, Gilbert M. Wolrich | 2008-09-16 |
| 7415027 | Processing frame bits | — | 2008-08-19 |
| 7243214 | Stall optimization for an in-order, multi-stage processor pipeline which analyzes current and next instructions to determine if a stall is necessary | Niall D. McDonnell | 2007-07-10 |
| 7007156 | Multiple coprocessor architecture to process a plurality of subtasks in parallel | Gavin J. Stark | 2006-02-28 |
| 6981113 | Storage registers for a processor pipeline | Niall D. McDonnell | 2005-12-27 |
| 6963535 | MAC bus interface | Gavin J. Stark | 2005-11-08 |
| 6901507 | Context scheduling | — | 2005-05-31 |
| 6874080 | Context processing by substantially simultaneously selecting address and instruction of different contexts | — | 2005-03-29 |
| 6826676 | Extending immediate operands across plural computer instructions with indication of how many instructions are used to store the immediate operand | — | 2004-11-30 |
| 5864716 | Tagged data compression for parallel port interface | — | 1999-01-26 |
| 5781799 | DMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllers | Geary L. Leger, Bhoopal R. Benjaram, Peter R. Carpenter, Gary L. Schaps | 1998-07-14 |
| 5765023 | DMA controller having multiple channels and buffer pool having plurality of buffers accessible to each channel for buffering data transferred to and from host computer | Geary L. Leger, Bhoopal R. Benjaram, Peter R. Carpenter, Gary L. Schaps | 1998-06-09 |
| 5588145 | Method and arrangement for clock adjustment using programmable period binary rate multiplier | — | 1996-12-24 |
| 5566352 | Register-read acknowledgment and prioritization for integration with a hardware-based interrupt acknowledgment mechanism | — | 1996-10-15 |
| 4975828 | Multi-channel data communications controller | Cecil H. Kaplinsky, Anthony J. P. O'Toole, Shahin Hedayat, Shrikant Acharya | 1990-12-04 |
| 4254477 | Reconfigurable memory circuit | Yukun Hsia | 1981-03-03 |