Issued Patents All Time
Showing 25 most recent of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10911038 | Configuration mesh data bus and transactional memories in a multi-processor integrated circuit | Steven W. Zagorianakos, Ronald N. Fortino | 2021-02-02 |
| 10853074 | Table fetch processor instruction using table number to base address translation | — | 2020-12-01 |
| 10659030 | Transactional memory that performs a statistics add-and-update operation | Benjamin J. Cahill | 2020-05-19 |
| 10474465 | Pop stack absolute instruction | — | 2019-11-12 |
| 10365681 | Multiprocessor system having fast clocking prefetch circuits that cause processor clock signals to be gapped | — | 2019-07-30 |
| 10366019 | Multiprocessor system having efficient and shared atomic metering resource | — | 2019-07-30 |
| 10362093 | NFA completion notification | Steven W. Zagorianakos | 2019-07-23 |
| 10230638 | Executing a selected sequence of instructions depending on packet type in an exact-match flow switch | Stuart Wray | 2019-03-12 |
| 10228968 | Network interface device that alerts a monitoring processor if configuration of a virtual NID is changed | Rolf Neugebauer | 2019-03-12 |
| 10191867 | Multiprocessor system having posted transaction bus interface that generates posted transaction bus commands | — | 2019-01-29 |
| 10146468 | Addressless merge command with data item identifier | Salma Mirza | 2018-12-04 |
| 10033638 | Executing a selected sequence of instructions depending on packet type in an exact-match flow switch | Stuart Wray | 2018-07-24 |
| 10031878 | Configurable mesh data bus in an island-based network flow processor | — | 2018-07-24 |
| 10031755 | Kick-started run-to-completion processing method that does not involve an instruction counter | — | 2018-07-24 |
| 10031754 | Kick-started run-to-completion processor having no instruction counter | — | 2018-07-24 |
| 10009270 | Modular and partitioned SDN switch | Stuart Wray | 2018-06-26 |
| 9998374 | Method of handling SDN protocol messages in a modular and partitioned SDN switch | Stuart Wray | 2018-06-12 |
| 9971720 | Distributed credit FIFO link of a configurable mesh data bus | Steven W. Zagorianakos, Ronald N. Fortino | 2018-05-15 |
| 9940097 | Registered FIFO | Ronald N. Fortino, Steven W. Zagorianakos | 2018-04-10 |
| 9912591 | Flow switch IC that uses flow IDs and an exact-match flow table | Stuart Wray | 2018-03-06 |
| 9900090 | Inter-packet interval prediction learning algorithm | Nicolaas J. Viljoen, Niel Viljoen | 2018-02-20 |
| 9899996 | Recursive lookup with a hardware trie structure that has no sequential logic elements | Bruce Wilford | 2018-02-20 |
| 9887918 | Intelligent packet data register file that stalls picoengine and retrieves data from a larger buffer | — | 2018-02-06 |
| 9866480 | Hash range lookup command | Hetal Sanket Borad, Ron Lamar Swartzentruber | 2018-01-09 |
| 9854072 | Script-controlled egress packet modifier | Chirag P. Patel | 2017-12-26 |