Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8598009 | Self-aligned embedded SiGe structure and method of manufacturing the same | Brian J. Greene, William K. Henson, Judson R. Holt, Kuldeep Amarnath, Rohit Pal +1 more | 2013-12-03 |
| 8232186 | Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure | Eric C. Harley, Judson R. Holt, Dominic J. Schepis, Linda Black, Rick Carter | 2012-07-31 |
| 8222673 | Self-aligned embedded SiGe structure and method of manufacturing the same | Brian J. Greene, William K. Henson, Judson R. Holt, Kuldeep Amarnath, Rohit Pal +1 more | 2012-07-17 |
| 7911024 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Herbert L. Ho, Mahender Kumar, Qiqing C. Ouyang, Paul A. Papworth, Christopher D. Sheraw | 2011-03-22 |
| 7763518 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Herbert L. Ho, Mahender Kumar, Qiqing C. Ouyang, Paul A. Papworth, Christopher D. Sheraw | 2010-07-27 |
| 7691716 | Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation | Herbert L. Ho, Mahender Kumar, Qiging Ouyang, Paul A. Papworth, Christopher D. Sheraw | 2010-04-06 |
| 7485537 | Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness | Herbert L. Ho, Mahender Kumar, Qiqing C. Ouyang, Paul A. Papworth, Christopher D. Sheraw | 2009-02-03 |
| 7394131 | STI formation in semiconductor device including SOI and bulk silicon regions | Mahender Kumar, Herbert L. Ho, David M. Dobuzinsky, Johnathan E. Faltermeier, Denise Pendleton | 2008-07-01 |
| 7375410 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Herbert L. Ho, Mahender Kumar, Qiqing C. Ouyang, Paul A. Papworth, Christopher D. Sheraw | 2008-05-20 |
| 7118986 | STI formation in semiconductor device including SOI and bulk silicon regions | Mahender Kumar, Herbert L. Ho, David M. Dobuzinsky, Johnathan E. Faltermeier, Denise Pendleton | 2006-10-10 |
| 7115463 | Patterning SOI with silicon mask to create box at different depths | Devendra K. Sadana, Dominic J. Schepis | 2006-10-03 |
| 7115965 | Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation | Herbert L. Ho, Mahender Kumar, Qiqing C. Ouyang, Paul A. Papworth, Christopher D. Sheraw | 2006-10-03 |
| 6995094 | Method for deep trench etching through a buried insulator layer | Herbert L. Ho, Mahender Kumar, Brian W. Messenger | 2006-02-07 |
| 6964897 | SOI trench capacitor cell incorporating a low-leakage floating body array transistor | Karen Bard, David M. Dobuzinsky, Herbert L. Ho, Mahendar Kumar, Denise Pendleton +1 more | 2005-11-15 |
| 6900092 | Surface engineering to prevent epi growth on gate poly during selective epi processing | Atul Ajmera, Dominic J. Schepis | 2005-05-31 |
| 6440807 | Surface engineering to prevent EPI growth on gate poly during selective EPI processing | Atul Ajmera, Dominic J. Schepis | 2002-08-27 |