Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7091128 | Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs | Atul Ajmera, Andres Bryant, Michael A. Gribelyuk, Edward P. Maciejewski, Renee T. Mo +1 more | 2006-08-15 |
| 6991979 | Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs | Atul Ajmera, Andres Bryant, Michael A. Gribelyuk, Edward P. Maciejewski, Renee T. Mo +1 more | 2006-01-31 |
| 6806584 | Semiconductor device structure including multiple fets having different spacer widths | Ka-Hing Fung | 2004-10-19 |
| 6362071 | Method for forming a semiconductor device with an opening in a dielectric layer | Bich-Yen Nguyen, William J. Taylor, Jr., Philip J. Tobin, David L. O'Meara, Yeong-Jyh T. Lii +1 more | 2002-03-26 |
| 5885856 | Integrated circuit having a dummy structure and method of making | Subramoney Iyer, Bradley P. Smith, Matthew A. Thompson, Kevin Kemp, Rajive Dhar | 1999-03-23 |
| 5773326 | Method of making an SOI integrated circuit with ESD protection | Paul G. Y. Tsui, Stephen G. Jamison, James W. Miller | 1998-06-30 |
| 5744841 | Semiconductor device with ESD protection | Paul G. Y. Tsui, Shih-Wei Sun, Stephen G. Jamison | 1998-04-28 |
| 5733794 | Process for forming a semiconductor device with ESD protection | Paul G. Y. Tsui, Shih-Wei Sun, Stephen G. Jamison | 1998-03-31 |
| 5708288 | Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method | John H. Quigley, Jeremy C. Smith, Shih-Wei Sun | 1998-01-13 |
| 5349224 | Integrable MOS and IGBT devices having trench gate structure | Gerold W. Neudeck | 1994-09-20 |