Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10170304 | Self-aligned nanotube structures | Oh-Jung Kwon, Claude Ortolland, Dominic J. Schepis | 2019-01-01 |
| 10170337 | Implant after through-silicon via (TSV) etch to getter mobile ions | Mukta G. Farooq, Troy L. Graves-Abe, Brian J. Greene, Robert Hannon, Herbert L. Ho +1 more | 2019-01-01 |
| 9252133 | Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures | Mukta G. Farooq, Troy L. Graves-Abe, Joyce C. Liu, Gerd Pfeiffer, Thuy L. Tran-Quinn | 2016-02-02 |
| 8907494 | Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures | Mukta G. Farooq, Troy L. Graves-Abe, Joyce C. Liu, Gerd Pfeiffer, Thuy L. Tran-Quinn | 2014-12-09 |
| 6440813 | Process of manufacturing a DRAM cell capacitor having increased trench capacitance | Harris C. Jones, James P. Norum, Stefan Schmitz | 2002-08-27 |
| 6328041 | Universal cleaning wafer for a plasma chamber | Jeffrey J. Brown, Wilson Tong Lee, George A. Kaplita, Stefan Schmitz, Len Yuan Tsou | 2001-12-11 |
| 6188096 | DRAM cell capacitor having increased trench capacitance | Harris C. Jones, James P. Norum, Stefan Schmitz | 2001-02-13 |
| 5948193 | Process for fabricating a multilayer ceramic substrate from thin greensheet | Michael A. Cohn, Jon A. Casey, Robert A. Rita, Robert J. Sullivan, Adrienne M. Tirch +2 more | 1999-09-07 |
| 5874162 | Weighted sintering process and conformable load tile | Kurt E. Bastian, James J. Burte, Michael A. Cohn, Joseph P. DeGeorge, Italo A. DiNunzio +5 more | 1999-02-23 |
| 5741131 | Stacking system for substrates | Joseph P. DeGeorge, Kurt E. Bastian, Michael A. Cohn, Italo A. DiNunzio, Ryan Wuthrich | 1998-04-21 |