Issued Patents All Time
Showing 1–25 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10529724 | Method of manufacturing a vertical SRAM with cross-coupled contacts penetrating through common gate structures | Hui Zang, Kwan-Yong Lim | 2020-01-07 |
| 10483172 | Transistor device structures with retrograde wells in CMOS applications | Vara Govindeswara Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna +2 more | 2019-11-19 |
| 10424584 | Semiconductor memory devices having an undercut source/drain region | Hui Zang | 2019-09-24 |
| 10290654 | Circuit structures with vertically spaced transistors and fabrication methods | Hui Zang, Min-hwa Chi | 2019-05-14 |
| 10249616 | Methods of forming a resistor structure between adjacent transistor gates on an integrated circuit product and the resulting devices | Hui Zang, Haiting Wang, Daniel Jaeger | 2019-04-02 |
| 10243059 | Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins | Srikanth Balaji Samavedan, Min-hwa Chi, Hui Zang | 2019-03-26 |
| 10157927 | Semiconductor memory devices having an undercut source/drain region | Hui Zang | 2018-12-18 |
| 10147802 | FINFET circuit structures with vertically spaced transistors and fabrication methods | Hui Zang, Min-hwa Chi | 2018-12-04 |
| 10121893 | Integrated circuit structure without gate contact and method of forming same | Hui Zang, Min-hwa Chi, Jerome Ciavatti | 2018-11-06 |
| 10089430 | Integrated circuits and methods of design and manufacture thereof | Henning Haffner, Richard Lindsay | 2018-10-02 |
| 10083971 | Vertical SRAM structure with cross-coupling contacts penetrating through common gates to bottom S/D metal contacts | Hui Zang, Kwan-Yong Lim | 2018-09-25 |
| 10056468 | Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins | Srikanth Balaji Samavedan, Min-hwa Chi, Hui Zang | 2018-08-21 |
| 9917191 | Semiconductor devices and methods of manufacture thereof | Jin-Ping Han | 2018-03-13 |
| 9852954 | Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures | Vara Govindeswara Reddy Vakada, Laegu Kang, Michael Ganz, Yi Qi, Puneet Khanna +2 more | 2017-12-26 |
| 9842927 | Integrated circuit structure without gate contact and method of forming same | Hui Zang, Min-hwa Chi, Jerome Ciavatti | 2017-12-12 |
| 9824748 | SRAM bitcell structures facilitating biasing of pull-up transistors | Hui Zang, Min-hwa Chi | 2017-11-21 |
| 9799661 | SRAM bitcell structures facilitating biasing of pull-down transistors | Hui Zang, Min-hwa Chi | 2017-10-24 |
| 9767244 | Integrated circuits and methods of design and manufacture thereof | Henning Haffner, Richard Lindsay | 2017-09-19 |
| 9734897 | SRAM bitcell structures facilitating biasing of pass gate transistors | Hui Zang, Min-hwa Chi | 2017-08-15 |
| 9601512 | SOI-based semiconductor device with dynamic threshold voltage | Hui Zang | 2017-03-21 |
| 9576952 | Integrated circuits with varying gate structures and fabrication methods | Manoj Joshi, Richard J. Carter, Srikanth B. Samavedam | 2017-02-21 |
| 9570586 | Fabrication methods facilitating integration of different device architectures | Hong Yu, Seong Yeol Mun, Bingwu Liu, Lun Zhao, Richard J. Carter | 2017-02-14 |
| 9543297 | Fin-FET replacement metal gate structure and method of manufacturing the same | Xusheng Wu, Konstantin G. Korablev, Shesh Mani Pandey | 2017-01-10 |
| 9484417 | Methods of forming doped transition regions of transistor structures | Xusheng Wu | 2016-11-01 |
| 9455201 | Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits | Manoj Joshi, Rohit Pal, Richard J. Carter, Srikanth B. Samavedam, Bongki Lee +1 more | 2016-09-27 |