Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8635575 | System and method to improve chip yield, reliability and performance | — | 2014-01-21 |
| 8185859 | System and method to improve chip yield, reliability and performance | — | 2012-05-22 |
| 7941780 | Intersect area based ground rule for semiconductor design | Albrik Avanessian, Dureseti Chidambarrao, Stephen E. Greco, Douglas W. Kemerer, Tina Wagner | 2011-05-10 |
| 7712057 | Determining allowance antenna area as function of total gate insulator area for SOI technology | Terence B. Hook, William F. Pokorny, Jeffrey S. Zimmerman | 2010-05-04 |
| 7299426 | System and method to improve chip yield, reliability and performance | — | 2007-11-20 |
| 7275226 | Method of performing latch up check on an integrated circuit design | David C. Reynolds, James E. Sundquist | 2007-09-25 |
| 7132318 | Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage | David L. Harmon, Terence B. Hook, Wing L. Lai | 2006-11-07 |
| 7120887 | Cloned and original circuit shape merging | Michael S. Gray, Jason D. Hibbeler, Kevin W. McCullen, Robert F. Walker | 2006-10-10 |
| 7067886 | Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage | David L. Harmon, Terence B. Hook, Wing L. Lai | 2006-06-27 |
| 5313424 | Module level electronic redundancy | Robert Dean Adams, James Dawson, Erik L. Hedberg | 1994-05-17 |
| 5101120 | BiCMOS output driver | Roy C. Flaker | 1992-03-31 |