Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7823103 | Method and system of introducing hierarchy into design rule checking test cases and rotation of test case data | — | 2010-10-26 |
| 7712057 | Determining allowance antenna area as function of total gate insulator area for SOI technology | Henry A. Bonges, III, Terence B. Hook, Jeffrey S. Zimmerman | 2010-05-04 |
| 7478348 | Method and apparatus of rapid determination of problematic areas in VLSI layout by oriented sliver sampling | — | 2009-01-13 |
| 6629292 | Method for forming graphical images in semiconductor devices | Phillip L. Corson, Gary R. Holsopple, Jason Parry | 2003-09-30 |
| 6262911 | Method to statically balance SOI parasitic effects, and eight device SRAM cells using same | Geordie M. Braceras, Alan L. Roberts | 2001-07-17 |
| 6243854 | Method for selecting hierarchical interactions in a hierarchical shapes processor | Mark A. Lavin, Robert T. Sayah, Young Ouk Kim | 2001-06-05 |
| 6026224 | Redundant vias | Laura R. Darden, William J. Livingstone, Jeannie H. Panner, Patrick E. Perry, Paul S. Zuchowski | 2000-02-15 |