Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10810348 | Constructing colorable wiring layouts with wide wires and sandwich rules | — | 2020-10-20 |
| 10755017 | Cell placement in a circuit with shared inputs and outputs | Brent A. Anderson, Albert M. Chu, Alexander J. Suess | 2020-08-25 |
| 10586009 | Hierarchical trim management for self-aligned double patterning | David Wolpert | 2020-03-10 |
| 7725850 | Methods for design rule checking with abstracted via obstructions | William J. Livingstone | 2010-05-25 |
| 7278127 | Overlapping shape design rule error prevention | Mark R. Lasher | 2007-10-02 |
| 6779165 | Spacing violation checker | — | 2004-08-17 |
| 6598206 | Method and system of modifying integrated circuit power rails | Scott Whitney Gould, Patrick M. Ryan, Steven J. Urish | 2003-07-22 |
| 6301689 | Spacing violation checker | — | 2001-10-09 |
| 6185722 | Three dimensional track-based parasitic extraction | James Engel, Peter A. Habitz, William J. Livingstone, Daniel Joseph Mainiero, Jeannie H. Panner +2 more | 2001-02-06 |
| 6026224 | Redundant vias | William J. Livingstone, Jeannie H. Panner, Patrick E. Perry, William F. Pokorny, Paul S. Zuchowski | 2000-02-15 |