Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412020 | Effective metal density screens for hierarchical design rule checking (DRC) analysis | Brian Veraa, Ryan Michael Kruse, Christopher Gonzalez | 2025-09-09 |
| 12381149 | Cell optimization through source resistance improvement | Leon Sigal, Bharat Biyani | 2025-08-05 |
| 12382621 | Decoupling capacitor inside gate cut trench | Reinaldo Vega, Takashi Ando, Praneet Adusumilli, Cheng Chi | 2025-08-05 |
| 12362278 | Transistors with dual power and signal lines | Tao Li, Ruilong Xie, Albert M. Chu | 2025-07-15 |
| 12271674 | Generating a power delivery network based on the routing of signal wires within a circuit design | Matthew T. Guzowski, Michael H. Wood, Leon Sigal | 2025-04-08 |
| 12266393 | Negative capacitance for ferroelectric capacitive memory cell | Takashi Ando, Reinaldo Vega, Nicholas Anthony Lanzillo | 2025-04-01 |
| 12176289 | Semiconductor device design mitigating latch-up | Leon Sigal, Terence B. Hook | 2024-12-24 |
| 12112114 | Hierarchical color decomposition of library cells with boundary-aware color selection | Leon Sigal, Michael S. Gray, Mitchell R. DeHond | 2024-10-08 |
| 12057387 | Decoupling capacitor inside gate cut trench | Reinaldo Vega, Takashi Ando, Praneet Adusumilli, Cheng Chi | 2024-08-06 |
| 11941340 | Cross-hierarchy antenna condition verification | Michael Alexander Bowen, Gerald Strevig, III, Amanda Christine Venton, Robert M. Averill, III, Adam P. Matheny +1 more | 2024-03-26 |
| 11916099 | Multilayer dielectric for metal-insulator-metal capacitor | Takashi Ando, Reinaldo Vega, Cheng Chi, Praneet Adusumilli | 2024-02-27 |
| 11916384 | Region-based power grid generation through modification of an initial power grid based on timing analysis | Basanth Jagannathan, Michael H. Wood, Leon Sigal, James Leland, Alexander J. Suess +2 more | 2024-02-27 |
| 11906570 | Processor frequency improvement based on antenna optimization | Christopher Gonzalez, Michael H. Wood | 2024-02-20 |
| 11830778 | Back-side wafer modification | Daniel James Dechene, Lawrence A. Clevenger, Michael Romain, Somnath Ghosh | 2023-11-28 |
| 11822867 | Hierarchical color decomposition of process layers with shape and orientation requirements | Leon Sigal, Michael S. Gray, Mitchell R. DeHond | 2023-11-21 |
| 11754615 | Processor frequency improvement based on antenna optimization | Christopher Gonzalez, Michael H. Wood | 2023-09-12 |
| 11663391 | Latch-up avoidance for sea-of-gates | Ryan Michael Kruse, Leon Sigal, Richard Edward Serton, Matthew S. Angyal, Terence B. Hook +1 more | 2023-05-30 |
| 11586798 | Avoiding electrostatic discharge events from cross-hierarchy tie nets | Brian Veraa, Ryan Michael Kruse, Christopher Gonzalez | 2023-02-21 |
| 11487308 | Ensuring IoT device functionality in the presence of multiple temperature dependencies | Haard Kamlesh Mehta | 2022-11-01 |
| 11308257 | Stacked via rivets in chip hotspots | Dureseti Chidambarrao, Atsushi Ogino, Matthew T. Guzowski, Steven P. Ostrander, Tuhin Sinha +1 more | 2022-04-19 |
| 11106850 | Flexible constraint-based logic cell placement | Timothy A. Schell, Erwin Behnen, Leon Sigal | 2021-08-31 |
| 11055465 | Fill techniques for avoiding Boolean DRC failures during cell placement | Timothy A. Schell, Michael S. Gray, Erwin Behnen, Robert M. Averill, III | 2021-07-06 |
| 10896283 | Noise-based optimization for integrated circuit design | Kyle Indukummar Giesen, Samuel Sagan | 2021-01-19 |
| 10885260 | Fin-based fill cell optimization | Timothy A. Schell, Michael S. Gray, Erwin Behnen, Robert M. Averill, III | 2021-01-05 |
| 10831980 | Using unused wires on very-large-scale integration chips for power supply decoupling | Alan P. Wagstaff | 2020-11-10 |