Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11106850 | Flexible constraint-based logic cell placement | David Wolpert, Timothy A. Schell, Leon Sigal | 2021-08-31 |
| 11055465 | Fill techniques for avoiding Boolean DRC failures during cell placement | David Wolpert, Timothy A. Schell, Michael S. Gray, Robert M. Averill, III | 2021-07-06 |
| 10885260 | Fin-based fill cell optimization | David Wolpert, Timothy A. Schell, Michael S. Gray, Robert M. Averill, III | 2021-01-05 |
| 10699050 | Front-end-of-line shape merging cell placement and optimization | David Wolpert, Lawrence A. Clevenger, Patrick Watson, Chih-Chao Yang, Timothy A. Schell | 2020-06-30 |
| 10248749 | Automated attribute propagation and hierarchical consistency checking for non-standard extensions | Robert M. Averill, III, David Wolpert | 2019-04-02 |
| 10223487 | Automated attribute propagation and hierarchical consistency checking for non-standard extensions | Robert M. Averill, III, David Wolpert | 2019-03-05 |
| 9977851 | Automated attribute propagation and hierarchical consistency checking for non-standard extensions | Robert M. Averill, III, David Wolpert | 2018-05-22 |
| 9971861 | Selective boundary overlay insertion for hierarchical circuit design | Michael S. Gray, Matthew T. Guzowski, David Wolpert | 2018-05-15 |
| 9892222 | Automated attribute propagation and hierarchical consistency checking for non-standard extensions | Robert M. Averill, III, David Wolpert | 2018-02-13 |
| 7225419 | Methods for modeling latch transparency | Jeffrey P. Soreff, James D. Warnock, Dieter Wendel | 2007-05-29 |
| 7080335 | Methods for modeling latch transparency | Jeffrey P. Soreff, James D. Warnock, Dieter Wendel | 2006-07-18 |