Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11941340 | Cross-hierarchy antenna condition verification | Gerald Strevig, III, Amanda Christine Venton, Robert M. Averill, III, Adam P. Matheny, David Wolpert +1 more | 2024-03-26 |
| 11922109 | Predictive antenna diode insertion | Amanda Christine Venton, Rahul M. Rao | 2024-03-05 |
| 11341311 | Generation and selection of universally routable via mesh specifications in an integrated circuit | Joseph KOONE, Smitha REDDY, Gustavo E. Tellez, Adam P. Matheny | 2022-05-24 |
| 7921399 | Method for simplifying tie net modeling for router performance | Christopher J. Berry | 2011-04-05 |
| 7844435 | Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques | Alina Deutsch, Gerard V. Kopcsay, Byron L. Krauter, Barry J. Rubin, Howard H. Smith +1 more | 2010-11-30 |
| 7681169 | Process for managing complex pre-wired net segments in a VLSI design | Christopher J. Berry, Michael R. Scheuermann, Michael H. Wood | 2010-03-16 |
| 7319946 | Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques | Alina Deutsch, Gerard V. Kopcsay, Byron L. Krauter, Barry J. Rubin, Howard H. Smith +1 more | 2008-01-15 |
| 6546529 | Method for performing coupling analysis | Allan H. Dansky, Peter J. Camporese, Alina Deutsch, Howard H. Smith | 2003-04-08 |
| 6338025 | Data processing system and method to estimate power in mixed dynamic/static CMOS designs | Byron L. Krauter, Steven Schmidt, Clay Chip Smith, Amy May Tuvell | 2002-01-08 |
| 6279142 | Method of on-chip interconnect design | Moises Cases, Howard H. Smith | 2001-08-21 |
| 6028989 | Calculating crosstalk voltage from IC craftsman routing data | Allan H. Dansky, Howard H. Smith, Fadi Y. Busaba, Adrian Zuckerman | 2000-02-22 |