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Method for evaluating decoupling capacitor placement for VLSI chips |
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2003-09-09 |
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Method for evaluating decoupling capacitor placement for VLSI chips |
Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman +1 more |
2003-09-09 |
| 6546529 |
Method for performing coupling analysis |
Michael Alexander Bowen, Peter J. Camporese, Alina Deutsch, Howard H. Smith |
2003-04-08 |
| 6460169 |
Routing program method for positioning unit pins in a hierarchically designed VLSI chip |
Peter J. Camporese, Howard H. Smith |
2002-10-01 |
| 6418401 |
Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation |
Alina Deutsch, Gerard V. Kopcsay, Phillip J. Restle, Howard H. Smith |
2002-07-09 |
| 6415428 |
Minimal length method for positioning unit pins in a hierarchically designed VLSI chip |
Peter J. Camporese, Howard H. Smith |
2002-07-02 |
| 6374394 |
Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip |
Peter J. Camporese, Howard H. Smith |
2002-04-16 |
| 6342823 |
System and method for reducing calculation complexity of lossy, frequency-dependent transmission-line computation |
Alina Deutsch, Gerard V. Kopcsay, Phillip J. Restle, Howard H. Smith |
2002-01-29 |
| 6323050 |
Method for evaluating decoupling capacitor placement for VLSI chips |
Wiren D. Becker, Howard H. Smith, Peter J. Camporese, Kwok Fai Eng, Dale E. Hoffman +1 more |
2001-11-27 |
| 6028989 |
Calculating crosstalk voltage from IC craftsman routing data |
Howard H. Smith, Fadi Y. Busaba, Michael Alexander Bowen, Adrian Zuckerman |
2000-02-22 |
| 5287016 |
High-speed bipolar-field effect transistor (BI-FET) circuit |
John F. McCabe, Kenny K. Shin |
1994-02-15 |
| 5166552 |
Multi-emitter BICMOS logic circuit family with superior performance |
Anthony Gus Aipperspach, Gerard Boudon, Pierre Mollier, Ieng Ong, Nghia V. Phan +3 more |
1992-11-24 |
| 5121001 |
Low power push-pull driver |
Allan L. Mullgrav, Jr. |
1992-06-09 |
| 5030856 |
Receiver and level converter circuit with dual feedback |
Chris J. Rebeor, Dennis C. Reedy |
1991-07-09 |
| 4746817 |
BIFET logic circuit |
Dennis C. Banker, Jack A. Dorler, Walter S. Klara, Frank M. Masci, Steven J. Zier +1 more |
1988-05-24 |
| 4668879 |
"Dotted ""or"" function for current controlled gates" |
Martine M. F. Savalle, Helmut Schettler |
1987-05-26 |
| 4605870 |
High speed low power current controlled gate circuit |
John P. Norsworthy |
1986-08-12 |
