Issued Patents All Time
Showing 1–25 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7961932 | Method and apparatus for manufacturing diamond shaped chips | Robert J. Allen, John M. Cohn, Peter A. Habitz, Juergen Koehl, Gustavo E. Tellez +2 more | 2011-06-14 |
| 7496877 | Electrostatic discharge failure avoidance through interaction between floorplanning and power routing | Andrew D. Huber, Ciaran J. Brennan, Paul E. Dunn, Lin Lin, Erich C. Schanzenbach | 2009-02-24 |
| 7289659 | Method and apparatus for manufacturing diamond shaped chips | Robert J. Allen, John M. Cohn, Peter A. Habitz, Juergen Koehl, Gustavo E. Tellez +2 more | 2007-10-30 |
| 7234124 | Method and apparatus for performing power routing on a voltage island within an integrated circuit chip | Bing Chen, Mark Hsu, Patrick M. Ryan, Erich C. Schanzenbach | 2007-06-19 |
| 7131074 | Nested voltage island architecture | Thomas R. Bednar, David E. Lackey, Douglas W. Stout, Paul S. Zuchowski | 2006-10-31 |
| 7096436 | Macro design techniques to accommodate chip level wiring and circuit placement across the macro | Thomas R. Bednar, Paul E. Dunn, Jeannie H. Panner, Paul S. Zuchowski | 2006-08-22 |
| 6917430 | Method to improve the control of source chemicals delivery by a carrier gas | Michael Berman | 2005-07-12 |
| 6883152 | Voltage island chip implementation | Thomas R. Bednar, David E. Lackey, Douglas W. Stout, Paul S. Zuchowski | 2005-04-19 |
| 6883155 | Macro design techniques to accommodate chip level wiring and circuit placement across the macro | Thomas R. Bednar, Paul E. Dunn, Jeannie H. Panner, Paul S. Zuchowski | 2005-04-19 |
| 6861753 | Method and apparatus for performing power routing on a voltage island within an integrated circuit chip | Bing Chen, Mark Hsu, Patrick M. Ryan, Erich C. Schanzenbach | 2005-03-01 |
| 6832361 | System and method for analyzing power distribution using static timing analysis | John M. Cohn, Ronald D. Rose, Ivan L. Wemple, Paul S. Zuchowski | 2004-12-14 |
| 6825711 | Power reduction by stage in integrated circuit | John M. Cohn, Kenneth J. Goodnow, Douglas W. Stout, Sebastian T. Ventrone | 2004-11-30 |
| 6820240 | Voltage island chip implementation | Thomas R. Bednar, David E. Lackey, Douglas W. Stout, Paul S. Zuchowski | 2004-11-16 |
| 6802033 | Low-power critical error rate communications controller | Claude L. Bertin, Alvar A. Dean, Kenneth J. Goodnow, Patrick E. Perry, Wilbur D. Pricer +1 more | 2004-10-05 |
| 6779163 | Voltage island design planning | Thomas R. Bednar, David E. Lackey, Douglas W. Stout, Paul S. Zuchowski | 2004-08-17 |
| 6731154 | Global voltage buffer for voltage islands | Thomas R. Bednar, David E. Lackey, Douglas W. Stout, Paul S. Zuchowski | 2004-05-04 |
| 6598206 | Method and system of modifying integrated circuit power rails | Laura R. Darden, Patrick M. Ryan, Steven J. Urish | 2003-07-22 |
| 6543040 | Macro design techniques to accommodate chip level wiring and circuit placement across the macro | Thomas R. Bednar, Paul E. Dunn, Jeannie H. Panner, Paul S. Zuchowski | 2003-04-01 |
| 6493859 | Method of wiring power service terminals to a power network in a semiconductor integrated circuit | Philip S. Honsinger, Andrew D. Huber, Patrick M. Ryan | 2002-12-10 |
| 6490708 | Method of integrated circuit design by selection of noise tolerant gates | John M. Cohn, Peter A. Habitz, Jose L. Neves, William F. Smith, Larry Wissel +1 more | 2002-12-03 |
| 6425092 | Method and apparatus for preventing thermal failure in a semiconductor device through redundancy | Richard J. Evans, Anthony M. Palagonia, Sebastian T. Ventrone | 2002-07-23 |
| 6397170 | Simulation based power optimization | Alvar A. Dean, Kenneth J. Goodnow, Sebastian T. Ventrone | 2002-05-28 |
| 6345362 | Managing Vt for reduced power using a status table | Claude L. Bertin, Alvar A. Dean, Kenneth J. Goodnow, Wilbur D. Pricer, William R. Tonti +1 more | 2002-02-05 |
| 6237132 | Toggle based application specific core methodology | Alvar A. Dean, Kenneth J. Goodnow, Kenneth Torino, Sebastian T. Ventrone | 2001-05-22 |
| 6233191 | Field programmable memory array | Joseph A. Iadanza, Frank Ray Keyser, III | 2001-05-15 |