Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6134704 | Integrated circuit macro apparatus | John S. Adams, Grant L. Clarke, Jr., Kenneth J. Goodnow, Sebastian T. Ventrone | 2000-10-17 |
| 6130854 | Programmable address decoder for field programmable memory array | Joseph A. Iadanza, Frank Ray Keyser, III, Terrance John Zittritsch | 2000-10-10 |
| 6118707 | Method of operating a field programmable memory array with a field programmable gate array | Joseph A. Iadanza, Frank Ray Keyser, III, Terrance John Zittritsch | 2000-09-12 |
| 6075745 | Field programmable memory array | Joseph A. Iadanza, Frank Ray Keyser, III, Victor Paul Seidel, Terrance John Zittritsch | 2000-06-13 |
| 6023421 | Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array | Kim P. N. Clinton, Joseph A. Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie +2 more | 2000-02-08 |
| 6021513 | Testable programmable gate array and associated LSSD/deterministic test methodology | Wayne Kevin Beebe, Sally Botala, Frank Ray Keyser, III, Wendell Ray Larsen, Ronald Raymond Palmer +1 more | 2000-02-01 |
| 5949719 | Field programmable memory array | Kim P. N. Clinton, Joseph A. Iadanza, Frank Ray Keyser, III, Ralph David Kilmoyer, Michael Joseph Laramie +2 more | 1999-09-07 |
| 5910733 | Method and system for layout and schematic generation for heterogeneous arrays | Allan Robert Bertolet, Kim P. N. Clinton, Frank Ray Keyser III, Timothy Shawn Reny, Terrance John Zittritsch | 1999-06-08 |
| 5867507 | Testable programmable gate array and associated LSSD/deterministic test methodology | Wayne Kevin Beebe, Sally Botala, Frank Ray Keyser III, Wendell Ray Larsen, Ronald Raymond Palmer +1 more | 1999-02-02 |
| 5781032 | Programmable inverter circuit used in a programmable logic cell | Allan Robert Bertolet, Kim P. N. Clinton, Christine Marie Fuller, Steven Paul Hartman, Joseph A. Iadanza +6 more | 1998-07-14 |
| 5761078 | Field programmable gate arrays using semi-hard multicell macros | Christine Marie Fuller, Steven Paul Hartman, Eric Ernest Millham, Gulsun Yasar | 1998-06-02 |
| 5760611 | Function generator for programmable gate array | — | 1998-06-02 |
| 5748009 | Programmable logic cell | Allan Robert Bertolet, Kim P. N. Clinton, Christine Marie Fuller, Steven Paul Hartman, Joseph A. Iadanza +6 more | 1998-05-05 |
| 5745734 | Method and system for programming a gate array using a compressed configuration bit stream | David Craft, Frank Ray Keyser, III, Brian Worth | 1998-04-28 |
| 5734582 | Method and system for layout and schematic generation for heterogeneous arrays | Allan Robert Bertolet, Kim P. N. Clinton, Frank Ray Keyser, III, Timothy Shawn Reny, Terrance John Zittritsch | 1998-03-31 |
| 5732246 | Programmable array interconnect latch | Frank Ray Keyser, III, Wendell Ray Larsen, Brian Worth | 1998-03-24 |
| 5717346 | Low skew multiplexer network and programmable array clock/reset application thereof | Frederick Curtis Furtek, Frank Ray Keyser, III, Brian Worth, Terrance John Zittritsch | 1998-02-10 |
| 5703498 | Programmable array clock/reset resource | Frederick Curtis Furtek, Frank Ray Keyser, III, Brian Worth, Terrance John Zittritsch | 1997-12-30 |
| 5694057 | System for enhanced drive in programmable gate arrays | — | 1997-12-02 |
| 5671432 | Programmable array I/O-routing resource | Allan Robert Bertolet, Kenneth Ferguson, Eric Ernest Millham, Ronald Raymond Palmer, Brian Worth +1 more | 1997-09-23 |
| 5652529 | Programmable array clock/reset resource | Frederick Curtis Furtek, Frank Ray Keyser, III, Brian Worth, Terrance John Zittritsch | 1997-07-29 |
| 5646546 | Programmable logic cell having configurable gates and multiplexers | Allan Robert Bertolet, Kim P. N. Clinton, Christine Marie Fuller, Steven Paul Hartman, Joseph A. Iadanza +6 more | 1997-07-08 |
| 5631578 | Programmable array interconnect network | Kim P. N. Clinton, Steven Paul Hartman, Joseph A. Iadanza, Frank Ray Keyser, III, Eric Ernest Millham | 1997-05-20 |
| 5552721 | Method and system for enhanced drive in programmmable gate arrays | — | 1996-09-03 |
| 5341310 | Wiring layout design method and system for integrated circuits | Mark Gregory Marshall, Patrick E. Perry | 1994-08-23 |