Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6204074 | Chip design process for wire bond and flip-chip package | James Fiore, Eberhard Gramatzki | 2001-03-20 |
| 6025744 | Glitch free delay line multiplexing technique | Albert M. Chu, Frank D. Ferraiolo, Samuel Weinstein | 2000-02-15 |
| 5910733 | Method and system for layout and schematic generation for heterogeneous arrays | Kim P. N. Clinton, Scott Whitney Gould, Frank Ray Keyser III, Timothy Shawn Reny, Terrance John Zittritsch | 1999-06-08 |
| 5844317 | Consolidated chip design for wire bond and flip-chip package technologies | James Fiore, Eberhard Gramatski | 1998-12-01 |
| 5781032 | Programmable inverter circuit used in a programmable logic cell | Kim P. N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Joseph A. Iadanza +6 more | 1998-07-14 |
| 5748009 | Programmable logic cell | Kim P. N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Joseph A. Iadanza +6 more | 1998-05-05 |
| 5734582 | Method and system for layout and schematic generation for heterogeneous arrays | Kim P. N. Clinton, Scott Whitney Gould, Frank Ray Keyser, III, Timothy Shawn Reny, Terrance John Zittritsch | 1998-03-31 |
| 5671432 | Programmable array I/O-routing resource | Kenneth Ferguson, Scott Whitney Gould, Eric Ernest Millham, Ronald Raymond Palmer, Brian Worth +1 more | 1997-09-23 |
| 5646546 | Programmable logic cell having configurable gates and multiplexers | Kim P. N. Clinton, Christine Marie Fuller, Scott Whitney Gould, Steven Paul Hartman, Joseph A. Iadanza +6 more | 1997-07-08 |
| 5389836 | Branch isolation circuit for cascode voltage switch logic | Albert M. Chu, William R. Griffin, John G. Petrovick, Jr., Larry Wissel | 1995-02-14 |