IW

Ivan L. Wemple

IBM: 21 patents #5,175 of 70,183Top 8%
GE: 2 patents #13,562 of 36,430Top 40%
Overall (All Time): #185,160 of 4,157,543Top 5%
23
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8988140 Real-time adaptive voltage control of logic blocks Richard S. Graf, Joseph A. Iadanza, Faraydon Pakbaz, Jack R. Smith, Sebastian T. Ventrone 2015-03-24
8438520 Early decoupling capacitor optimization method for hierarchical circuit design Kurt A. Carlsen, Charles S. Chiu, Umberto Garofano, Ze Gui Pang, Eric W. Tremble +1 more 2013-05-07
8302063 Method and system to optimize semiconductor products for power, performance, noise, and cost through use of variable power supply voltage compression Jeanne P. Bickford, Umberto Garofano, James E. Jasmin, Tad J. Wilder 2012-10-30
8015526 Static timing slacks analysis and modification Thomas Chadwick, Margaret R. Charlebois, David J. Hathaway, Jason Rotella, Douglas W. Stout 2011-09-06
7961932 Method and apparatus for manufacturing diamond shaped chips Robert J. Allen, John M. Cohn, Scott Whitney Gould, Peter A. Habitz, Juergen Koehl +2 more 2011-06-14
7669159 IC tiling pattern method, IC so formed and analysis method Robert J. Allen, John M. Cohn, Peter A. Habitz, William C. Leipold, Paul S. Zuchowski 2010-02-23
7475366 Integrated circuit design closure method for selective voltage binning Mark W. Kuemerle, Susan K. Lichtensteiger, Douglas W. Stout 2009-01-06
7454305 Method and apparatus for storing circuit calibration information Anthony R. Bonaccio, Allen Haar, Joseph A. Iadanza, Douglas W. Stout 2008-11-18
7441213 Method for testing the validity of initial-condition statements in circuit simulation, and correcting inconsistencies thereof Timothy Lehner, Richard Daniel Kimmel, Ali Sadigh, Emrah Acar, Ying Liu 2008-10-21
7404163 Static timing slacks analysis and modification Thomas Chadwick, Margaret R. Charlebois, David J. Hathaway, Jason Rotella, Douglas W. Stout 2008-07-22
7289659 Method and apparatus for manufacturing diamond shaped chips Robert J. Allen, John M. Cohn, Scott Whitney Gould, Peter A. Habitz, Juergen Koehl +2 more 2007-10-30
7257788 Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits Allen Haar, Joseph A. Iadanza, Sebastian T. Ventrone 2007-08-14
7142991 Voltage dependent parameter analysis David J. Hathaway, Douglas W. Stout 2006-11-28
7000214 Method for designing an integrated circuit having multiple voltage domains Joseph A. Iadanza, Raminderpal Singh, Sebastian T. Ventrone 2006-02-14
6963240 Damping of LC ringing in IC (integrated circuit) power distribution systems Anthony R. Bonaccio, Allen Haar, Michael A. Sorna, Stephen D. Wyatt 2005-11-08
6948146 Simplified tiling pattern method Robert J. Allen, John M. Cohn, Peter A. Habitz, William C. Leipold, Paul S. Zuchowski 2005-09-20
6927616 Integrated circuit and method for interfacing two voltage domains using a transformer Shiu Chung Ho, Stephen D. Wyatt 2005-08-09
6832361 System and method for analyzing power distribution using static timing analysis John M. Cohn, Scott Whitney Gould, Ronald D. Rose, Paul S. Zuchowski 2004-12-14
6698008 Row-based placement scoring and legalization measure for books with phase shift mask dependencies Kevin W. McCullen 2004-02-24
6631502 Method of analyzing integrated circuit power distribution in chips containing voltage islands Patrick H. Buffet, Joseph N. Kozhaya, Paul D. Montane, Robert A. Proctor, Erich C. Schanzenbach 2003-10-07
6523154 Method for supply voltage drop analysis during placement phase of chip design John M. Cohn, James Venuto, Paul S. Zuchowski 2003-02-18
5010018 Method for forming Schottky photodiodes Kenneth J. Polasko 1991-04-23
4982246 Schottky photodiode with silicide layer Kenneth J. Polasko 1991-01-01