CC

Charles S. Chiu

IBM: 13 patents #8,581 of 70,183Top 15%
Overall (All Time): #385,196 of 4,157,543Top 10%
13
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8510697 System and method for modeling I/O simultaneous switching noise Erik Breiland, Prince George 2013-08-13
8438520 Early decoupling capacitor optimization method for hierarchical circuit design Kurt A. Carlsen, Umberto Garofano, Ze Gui Pang, Eric W. Tremble, David L. Toub +1 more 2013-05-07
8312404 Multi-segments modeling bond wire interconnects with 2D simulations in high speed, high density wire bond packages Haitian Hu, Timothy W. Budell, Eric W. Tremble 2012-11-13
8234611 System and method for modeling I/O simultaneous switching noise Erik Breiland, Prince George 2012-07-31
7809543 Method, apparatus and computer program product for electrical package modeling Craig Lussier 2010-10-05
7197446 Hierarchical method of power supply noise and signal integrity analysis Erik Breiland, Timothy W. Budell, Paul Lee Clouser, Charles K. Erdelyi, Brian Welch 2007-03-27
7110930 Integrated circuit and package modeling Umberto Garofano, James E. Jasmin 2006-09-19
7038319 Apparatus and method to reduce signal cross-talk Patrick H. Buffet, Jon Garlett, Louis L. Hsu, Brian J. Schuh 2006-05-02
7000203 Efficient and comprehensive method to calculate IC package or PCB trace mutual inductance using circular segments and lookup tables Patrick H. Buffet, Gustina B. Collins, Craig Lussier 2006-02-14
6598216 Method for enhancing a power bus in I/O regions of an ASIC device Francis Chan, Robert Cusimano, Donald S. Kent, Gulsun Yasar 2003-07-22
6584596 Method of designing a voltage partitioned solder-bump package Patrick H. Buffet, Yu Sun 2003-06-24
6584606 Fast method of I/O circuit placement and electrical rule checking James P. Libous, Rory D. Loughran, Joseph Natonio, Robert A. Proctor, Gulsun Yasar 2003-06-24
6523150 Method of designing a voltage partitioned wirebond package Patrick H. Buffet, Yu Sun 2003-02-18