| 7454723 |
Validation of electrical performance of an electronic package prior to fabrication |
Timothy W. Budell, Craig Lussier |
2008-11-18 |
$4,805,000 |
| 7146596 |
Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid |
Thomas R. Bednar, Timothy W. Budell, Alain Caron, James V. Crain, Jr., Douglas W. Kemerer +2 more |
2006-12-05 |
$6,328,000 |
| 7064570 |
Method for locating IDDQ defects using multiple controlled collapse chip connections current measurement on an automatic tester |
Douglas C. Heaberlin, Leah Pastel, Yu Sun |
2006-06-20 |
$5,983,000 |
| 7038319 |
Apparatus and method to reduce signal cross-talk |
Charles S. Chiu, Jon Garlett, Louis L. Hsu, Brian J. Schuh |
2006-05-02 |
$4,743,000 |
| 7017128 |
Concurrent electrical signal wiring optimization for an electronic package |
Jean Audet, Timothy W. Budell, Alain Caron |
2006-03-21 |
$6,971,000 |
| 7000203 |
Efficient and comprehensive method to calculate IC package or PCB trace mutual inductance using circular segments and lookup tables |
Charles S. Chiu, Gustina B. Collins, Craig Lussier |
2006-02-14 |
$5,958,000 |
| 6978214 |
Validation of electrical performance of an electronic package prior to fabrication |
Timothy W. Budell, Craig Lussier |
2005-12-20 |
$8,568,000 |
| 6924661 |
Power switch circuit sizing technique |
John M. Cohn, Kevin Grosselfinger, Susan K. Lichtensteiger, William F. Smith |
2005-08-02 |
$7,293,000 |
| 6762367 |
Electronic package having high density signal wires with low resistance |
Jean Audet, Timothy W. Budell |
2004-07-13 |
$8,966,000 |
| 6703706 |
Concurrent electrical signal wiring optimization for an electronic package |
Jean Audet, Timothy W. Budell, Alain Caron |
2004-03-09 |
$11,976,000 |
| 6677774 |
Method for locating IDDQ defects using multiple controlled collapse chip connections current measurement on an automatic tester |
Douglas C. Heaberlin, Leah Pastel, Yu Sun |
2004-01-13 |
$10,539,000 |
| 6631502 |
Method of analyzing integrated circuit power distribution in chips containing voltage islands |
Joseph N. Kozhaya, Paul D. Montane, Robert A. Proctor, Erich C. Schanzenbach, Ivan L. Wemple |
2003-10-07 |
$18,520,000 |
| 6606732 |
Method for specifying, identifying, selecting or verifying differential signal pairs on IC packages |
Craig Lussier, Joseph Natonio |
2003-08-12 |
$22,104,000 |
| 6586828 |
Integrated circuit bus grid having wires with pre-selected variable widths |
Yu Sun |
2003-07-01 |
$13,647,000 |
| 6584596 |
Method of designing a voltage partitioned solder-bump package |
Charles S. Chiu, Yu Sun |
2003-06-24 |
$21,997,000 |
| 6538314 |
Power grid wiring for semiconductor devices having voltage islands |
Yu Sun |
2003-03-25 |
$14,515,000 |
| 6523150 |
Method of designing a voltage partitioned wirebond package |
Charles S. Chiu, Yu Sun |
2003-02-18 |
$14,090,000 |
| 6499134 |
Method of assigning integrated circuit I/O signals in an integrated circuit package |
Paul E. Dunn, Joseph Natonio, Robert A. Proctor, Gulsun Yasar |
2002-12-24 |
$23,154,000 |
| 6495911 |
Scalable high frequency integrated circuit package |
Paul Lee Clouser, Danny Marvin Neal |
2002-12-17 |
$17,155,000 |
| 6483720 |
EMC protection in digital computers |
Paul Lee Clouser, Danny Marvin Neal |
2002-11-19 |
$21,860,000 |
| 6477057 |
High frequency de-coupling via short circuits |
Paul Lee Clouser, Danny Marvin Neal |
2002-11-05 |
$17,812,000 |
