Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7472364 | Method of matching layout shapes patterns in an integrated circuit using walsh patterns | Valerie D. Lehner | 2008-12-30 |
| 7441213 | Method for testing the validity of initial-condition statements in circuit simulation, and correcting inconsistencies thereof | Richard Daniel Kimmel, Ali Sadigh, Emrah Acar, Ying Liu, Ivan L. Wemple | 2008-10-21 |
| 6175947 | Method of extracting 3-D capacitance and inductance parasitics in sub-micron VLSI chip designs using pattern recognition and parameterization | Saila Ponnapalli, Sanjay Upreti | 2001-01-16 |