Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8024626 | Automation of fuse compression for an ASIC design system | Janice M. Adams, Frank Distler, Mark F. Ollive, Michael R. Ouellette | 2011-09-20 |
| 7174486 | Automation of fuse compression for an ASIC design system | Janice M. Adams, Frank Distler, Mark F. Ollive, Michael R. Ouellette | 2007-02-06 |
| 7096436 | Macro design techniques to accommodate chip level wiring and circuit placement across the macro | Thomas R. Bednar, Paul E. Dunn, Scott Whitney Gould, Paul S. Zuchowski | 2006-08-22 |
| 6931573 | Automated audit methodology for design | Janice M. Adams, Donald L. Hubbard, Bruce Raymond | 2005-08-16 |
| 6883155 | Macro design techniques to accommodate chip level wiring and circuit placement across the macro | Thomas R. Bednar, Paul E. Dunn, Scott Whitney Gould, Paul S. Zuchowski | 2005-04-19 |
| 6725439 | Method of automated design and checking for ESD robustness | Philip S. Homsinger, Andrew D. Huber, Debra K. Korejwa, William J. Livingstone, Erich C. Schanzenbach +3 more | 2004-04-20 |
| 6543040 | Macro design techniques to accommodate chip level wiring and circuit placement across the macro | Thomas R. Bednar, Paul E. Dunn, Scott Whitney Gould, Paul S. Zuchowski | 2003-04-01 |
| 6505324 | Automated fuse blow software system | Bruce Cowan, Frank Distler, Mark F. Ollive, Michael R. Ouellette, Dora R. Pealer +2 more | 2003-01-07 |
| 6185722 | Three dimensional track-based parasitic extraction | Laura R. Darden, James Engel, Peter A. Habitz, William J. Livingstone, Daniel Joseph Mainiero +2 more | 2001-02-06 |
| 6026224 | Redundant vias | Laura R. Darden, William J. Livingstone, Patrick E. Perry, William F. Pokorny, Paul S. Zuchowski | 2000-02-15 |
| 5751595 | Method for building and verifying authenticity of a rule system | Harry J. Beatty, III, Peter C. Elmendorf, Bijan Salimi, Lansing D. Pickup | 1998-05-12 |